tree bcc382418870b6fcb914781fa3ed12201bd827ef
parent 0cd2056c787a10959acb549cda10abc56f3bb5a7
parent 7004f6782e0c9c7c5875b294af049cd022695cbb
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> 1722961438 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1722961438 +0200

Merge changes from topic "enable_a53_clk" into integration

* changes:
  feat(nxp-clk): enable the A53 clock
  feat(nxp-clk): add ARM PLL ODIV enablement
  feat(nxp-clk): add ARM PLL enablement
  feat(nxp-clk): set rate for clock muxes