diff --git a/common/feat_detect.c b/common/feat_detect.c
index 7f01037..e6f827c 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -87,7 +87,7 @@
 {
 #if (ENABLE_RME == FEAT_STATE_ALWAYS)
 	feat_detect_panic((get_armv9_2_feat_rme_support() !=
-			ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
+			RME_NOT_IMPLEMENTED), "RME");
 #endif
 }
 
@@ -129,9 +129,10 @@
 	tainted = false;
 
 	/* v8.0 features */
-	check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1);
+	check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB",
+			SB_IMPLEMENTED, SB_IMPLEMENTED);
 	check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
-		      "CSV2_2", 2, 3);
+		      "CSV2_2", CSV2_2_IMPLEMENTED, CSV2_3_IMPLEMENTED);
 	/*
 	 * Even though the PMUv3 is an OPTIONAL feature, it is always
 	 * implemented and Arm prescribes so. So assume it will be there and do
@@ -142,25 +143,27 @@
 		      "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7);
 
 	/* v8.1 features */
-	check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
+	check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN",
+			PAN_IMPLEMENTED, PAN3_IMPLEMENTED);
 	check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1);
 
 	/* v8.2 features */
 	check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
-		      "SVE", 1, 1);
+		      "SVE", SVE_IMPLEMENTED, SVE_IMPLEMENTED);
 	check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
 
 	/* v8.3 features */
 	read_feat_pauth();
 
 	/* v8.4 features */
-	check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1);
+	check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT",
+			DIT_IMPLEMENTED, DIT_IMPLEMENTED);
 	check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
 		      "AMUv1", 1, 2);
 	check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
 		      "MPAM", 1, 17);
 	check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
-		      "NV2", 2, 2);
+		      "NV2", NV2_IMPLEMENTED, NV2_IMPLEMENTED);
 	check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
 		      "SEL2", 1, 1);
 	check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
@@ -177,19 +180,22 @@
 	check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
 		      "AMUv1p1", 2, 2);
 	check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), "FGT", 1, 1);
-	check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV", 1, 2);
+	check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), "ECV",
+			ECV_IMPLEMENTED, 2);
 	check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
-		      "TWED", 1, 1);
+		      "TWED", TWED_IMPLEMENTED, TWED_IMPLEMENTED);
 
 	/*
 	 * even though this is a "DISABLE" it does confusingly perform feature
 	 * enablement duties like all other flags here. Check it against the HW
 	 * feature when we intend to diverge from the default behaviour
 	 */
-	check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1);
+	check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU",
+			MTPMU_IMPLEMENTED, MTPMU_IMPLEMENTED);
 
 	/* v8.7 features */
-	check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1);
+	check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX",
+			HCX_IMPLEMENTED, HCX_IMPLEMENTED);
 
 	/* v8.9 features */
 	check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
@@ -207,15 +213,15 @@
 
 	/* v9.0 features */
 	check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
-		      "BRBE", 1, 2);
+		      "BRBE", BRBE_IMPLEMENTED, 2);
 	check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
 		      "TRBE", 1, 1);
 
 	/* v9.2 features */
 	check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
-		      "SME", 1, 2);
+		      "SME", SME_IMPLEMENTED, SME2_IMPLEMENTED);
 	check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
-		      "SME2", 2, 2);
+		      "SME2", SME2_IMPLEMENTED, SME2_IMPLEMENTED);
 
 	/* v9.4 features */
 	check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);