Merge "fix(spm): not defining load-address in SP config" into integration
diff --git a/Makefile b/Makefile
index e2de2c0..f8b230d 100644
--- a/Makefile
+++ b/Makefile
@@ -1244,6 +1244,7 @@
PSA_CRYPTO \
ENABLE_CONSOLE_GETC \
INIT_UNUSED_NS_EL2 \
+ PLATFORM_REPORT_CTX_MEM_USE \
)))
# Numeric_Flags
@@ -1437,8 +1438,16 @@
PSA_CRYPTO \
ENABLE_CONSOLE_GETC \
INIT_UNUSED_NS_EL2 \
+ PLATFORM_REPORT_CTX_MEM_USE \
)))
+ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1)
+ifeq (${DEBUG}, 0)
+ $(warning "PLATFORM_REPORT_CTX_MEM_USE can be applied when DEBUG=1 only")
+ override PLATFORM_REPORT_CTX_MEM_USE := 0
+endif
+endif
+
ifeq (${SANITIZE_UB},trap)
$(eval $(call add_define,MONITOR_TRAPS))
endif #(SANITIZE_UB)
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index f0776c4..40e3df8 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -61,6 +61,10 @@
BL31_SOURCES += $(DEBUGFS_SRCS)
endif
+ifeq (${PLATFORM_REPORT_CTX_MEM_USE},1)
+BL31_SOURCES += lib/el3_runtime/aarch64/context_debug.c
+endif
+
ifeq (${EL3_EXCEPTION_HANDLING},1)
BL31_SOURCES += bl31/ehf.c
endif
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 925c6a6..c8cc2c7 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -18,6 +18,7 @@
#include <common/runtime_svc.h>
#include <drivers/console.h>
#include <lib/bootmarker_capture.h>
+#include <lib/el3_runtime/context_debug.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/pmf/pmf.h>
#include <lib/runtime_instr.h>
@@ -106,6 +107,9 @@
*/
assert(is_armv8_3_pauth_present());
#endif /* CTX_INCLUDE_PAUTH_REGS */
+
+ /* Prints context_memory allocated for all the security states */
+ report_ctx_memory_usage();
}
/*******************************************************************************
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 3d409e3..5b03967 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -722,6 +722,11 @@
platform makefile named ``platform.mk``. For example, to build TF-A for the
Arm Juno board, select PLAT=juno.
+- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for
+ each core as well as the global context. The data includes the memory used
+ by each world and each privileged exception level. This build option is
+ applicable only for ``ARCH=aarch64`` builds. The default value is 0.
+
- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
instead of the normal boot flow. When defined, it must specify the entry
point address for the preloaded BL33 image. This option is incompatible with
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 202ef5c..117826d 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,7 +8,8 @@
#define NEOVERSE_POSEIDON_H
-#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
+#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
+#define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840)
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index cdcfa39..f637619 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -208,39 +208,39 @@
#define CTX_TFSR_EL2 U(0x100)
// Starting with Armv8.6
-#define CTX_HDFGRTR_EL2 U(0x160)
-#define CTX_HAFGRTR_EL2 U(0x168)
-#define CTX_HDFGWTR_EL2 U(0x170)
-#define CTX_HFGITR_EL2 U(0x178)
-#define CTX_HFGRTR_EL2 U(0x180)
-#define CTX_HFGWTR_EL2 U(0x188)
-#define CTX_CNTPOFF_EL2 U(0x190)
+#define CTX_HDFGRTR_EL2 U(0x108)
+#define CTX_HAFGRTR_EL2 U(0x110)
+#define CTX_HDFGWTR_EL2 U(0x118)
+#define CTX_HFGITR_EL2 U(0x120)
+#define CTX_HFGRTR_EL2 U(0x128)
+#define CTX_HFGWTR_EL2 U(0x130)
+#define CTX_CNTPOFF_EL2 U(0x138)
// Starting with Armv8.4
-#define CTX_CONTEXTIDR_EL2 U(0x198)
-#define CTX_TTBR1_EL2 U(0x1a0)
-#define CTX_VDISR_EL2 U(0x1a8)
-#define CTX_VSESR_EL2 U(0x1b0)
-#define CTX_VNCR_EL2 U(0x1b8)
-#define CTX_TRFCR_EL2 U(0x1c0)
+#define CTX_CONTEXTIDR_EL2 U(0x140)
+#define CTX_TTBR1_EL2 U(0x148)
+#define CTX_VDISR_EL2 U(0x150)
+#define CTX_VSESR_EL2 U(0x158)
+#define CTX_VNCR_EL2 U(0x160)
+#define CTX_TRFCR_EL2 U(0x168)
// Starting with Armv8.5
-#define CTX_SCXTNUM_EL2 U(0x1c8)
+#define CTX_SCXTNUM_EL2 U(0x170)
// Register for FEAT_HCX
-#define CTX_HCRX_EL2 U(0x1d0)
+#define CTX_HCRX_EL2 U(0x178)
// Starting with Armv8.9
-#define CTX_TCR2_EL2 U(0x1d8)
-#define CTX_POR_EL2 U(0x1e0)
-#define CTX_PIRE0_EL2 U(0x1e8)
-#define CTX_PIR_EL2 U(0x1f0)
-#define CTX_S2PIR_EL2 U(0x1f8)
-#define CTX_GCSCR_EL2 U(0x200)
-#define CTX_GCSPR_EL2 U(0x208)
+#define CTX_TCR2_EL2 U(0x180)
+#define CTX_POR_EL2 U(0x188)
+#define CTX_PIRE0_EL2 U(0x190)
+#define CTX_PIR_EL2 U(0x198)
+#define CTX_S2PIR_EL2 U(0x1a0)
+#define CTX_GCSCR_EL2 U(0x1a8)
+#define CTX_GCSPR_EL2 U(0x1b0)
/* Align to the next 16 byte boundary */
-#define CTX_EL2_SYSREGS_END U(0x210)
+#define CTX_EL2_SYSREGS_END U(0x1c0)
#endif /* CTX_INCLUDE_EL2_REGS */
diff --git a/include/lib/el3_runtime/context_debug.h b/include/lib/el3_runtime/context_debug.h
new file mode 100644
index 0000000..51e7748
--- /dev/null
+++ b/include/lib/el3_runtime/context_debug.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef CONTEXT_DEBUG_H
+#define CONTEXT_DEBUG_H
+
+#if PLATFORM_REPORT_CTX_MEM_USE && defined(__aarch64__)
+/********************************************************************************
+ * Reports the allocated memory for every security state and then reports the
+ * total system-wide allocated memory.
+ *******************************************************************************/
+void report_ctx_memory_usage(void);
+#else
+static inline void report_ctx_memory_usage(void) {}
+#endif /* PLATFORM_REPORT_CTX_MEM_USE */
+
+#endif /* CONTEXT_DEBUG_H */
diff --git a/include/plat/arm/board/common/rotpk/rotpk_def.h b/include/plat/arm/board/common/rotpk/rotpk_def.h
new file mode 100644
index 0000000..685c21a
--- /dev/null
+++ b/include/plat/arm/board/common/rotpk/rotpk_def.h
@@ -0,0 +1,24 @@
+
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROTPK_DEF_H
+#define ROTPK_DEF_H
+
+/*
+ * Definitions related to ROTPK
+ */
+
+/*
+ * Root of trust key lengths
+ */
+#ifndef ARM_ROTPK_HEADER_LEN
+#define ARM_ROTPK_HEADER_LEN 19
+#endif
+#ifndef ARM_ROTPK_HASH_LEN
+#define ARM_ROTPK_HASH_LEN 32
+#endif
+#endif /* ROTPK_DEF_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index e098c10..54b184d 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
@@ -19,11 +20,6 @@
* Definitions common to all ARM standard platforms
*****************************************************************************/
-/*
- * Root of trust key lengths
- */
-#define ARM_ROTPK_HEADER_LEN 19
-#define ARM_ROTPK_HASH_LEN 32
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index 1d3ac15..ecec5bc 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,38 @@
#include <platform_def.h>
+#ifdef __aarch64__
+#define SZ_32 UL(0x00000020)
+#define SZ_64 UL(0x00000040)
+#define SZ_128 UL(0x00000080)
+#define SZ_256 UL(0x00000100)
+#define SZ_512 UL(0x00000200)
+
+#define SZ_1K UL(0x00000400)
+#define SZ_2K UL(0x00000800)
+#define SZ_4K UL(0x00001000)
+#define SZ_8K UL(0x00002000)
+#define SZ_16K UL(0x00004000)
+#define SZ_32K UL(0x00008000)
+#define SZ_64K UL(0x00010000)
+#define SZ_128K UL(0x00020000)
+#define SZ_256K UL(0x00040000)
+#define SZ_512K UL(0x00080000)
+
+#define SZ_1M UL(0x00100000)
+#define SZ_2M UL(0x00200000)
+#define SZ_4M UL(0x00400000)
+#define SZ_8M UL(0x00800000)
+#define SZ_16M UL(0x01000000)
+#define SZ_32M UL(0x02000000)
+#define SZ_64M UL(0x04000000)
+#define SZ_128M UL(0x08000000)
+#define SZ_256M UL(0x10000000)
+#define SZ_512M UL(0x20000000)
+
+#define SZ_1G UL(0x40000000)
+#define SZ_2G UL(0x80000000)
+#else /* !__aarch64__ */
#define SZ_32 U(0x00000020)
#define SZ_64 U(0x00000040)
#define SZ_128 U(0x00000080)
@@ -42,6 +74,7 @@
#define SZ_1G U(0x40000000)
#define SZ_2G U(0x80000000)
+#endif /* __aarch64__ */
/******************************************************************************
* Required platform porting definitions that are expected to be common to
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
index 3b3245d..54c2ff9 100644
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -81,6 +81,10 @@
ret
endfunc neoverse_poseidon_cpu_reg_dump
-declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
+declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
+ neoverse_poseidon_reset_func, \
+ neoverse_poseidon_core_pwr_dwn
+
+declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn
diff --git a/lib/el3_runtime/aarch64/context_debug.c b/lib/el3_runtime/aarch64/context_debug.c
new file mode 100644
index 0000000..9ffa297
--- /dev/null
+++ b/lib/el3_runtime/aarch64/context_debug.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <context.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/el3_runtime/cpu_data.h>
+
+/********************************************************************************
+ * Function that returns the corresponding string constant for a security state
+ * index.
+ *******************************************************************************/
+static const char *get_context_name_by_idx(unsigned int security_state_idx)
+{
+ assert(security_state_idx < CPU_CONTEXT_NUM);
+ static const char * const state_names[] = {
+ "Secure",
+ "Non Secure"
+#if ENABLE_RME
+ , "Realm"
+#endif /* ENABLE_RME */
+ };
+ return state_names[security_state_idx];
+}
+
+#if CTX_INCLUDE_EL2_REGS
+#define PRINT_MEM_USAGE_SEPARATOR() \
+ do { \
+ printf("+-----------+-----------+-----------" \
+ "+-----------+-----------+-----------+\n"); \
+ } while (false)
+#else
+#define PRINT_MEM_USAGE_SEPARATOR() \
+ do { \
+ printf("+-----------+-----------" \
+ "+-----------+-----------+-----------+\n"); \
+ } while (false)
+#endif /* CTX_INCLUDE_EL2_REGS */
+
+#define NAME_PLACEHOLDER_LEN 14
+
+#define PRINT_DASH(n) \
+ for (; n > 0; n--) { \
+ putchar('-'); \
+ }
+
+/********************************************************************************
+ * This function prints the allocated memory for a specific security state.
+ * Values are grouped by exception level and core. The memory usage for the
+ * global context and the total memory for the security state are also computed.
+ *******************************************************************************/
+static size_t report_allocated_memory(unsigned int security_state_idx)
+{
+ size_t core_total = 0U;
+ size_t el3_total = 0U;
+#if CTX_INCLUDE_EL2_REGS
+ size_t el2_total = 0U;
+#endif /* CTX_INCLUDE_EL2_REGS */
+ size_t el1_total = 0U;
+ size_t other_total = 0U;
+ size_t total = 0U;
+ size_t per_world_ctx_size = 0U;
+
+ PRINT_MEM_USAGE_SEPARATOR();
+ printf("| Core | EL3 ");
+#if CTX_INCLUDE_EL2_REGS
+ printf("| EL2 ");
+#endif /* CTX_INCLUDE_EL2_REGS */
+ printf("| EL1 | Other | Total |\n");
+
+ /* Compute memory usage for each core's context */
+ for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) {
+ size_t size_other = 0U;
+ size_t el3_size = 0U;
+#if CTX_INCLUDE_EL2_REGS
+ size_t el2_size = 0U;
+#endif /* CTX_INCLUDE_EL2_REGS */
+ size_t el1_size = 0U;
+
+ PRINT_MEM_USAGE_SEPARATOR();
+ cpu_context_t *ctx = (cpu_context_t *)cm_get_context_by_index(i,
+ security_state_idx);
+ core_total = sizeof(*ctx);
+ el3_size = sizeof(ctx->el3state_ctx);
+#if CTX_INCLUDE_EL2_REGS
+ el2_size = sizeof(ctx->el2_sysregs_ctx);
+#endif /* CTX_INCLUDE_EL2_REGS */
+ el1_size = sizeof(ctx->el1_sysregs_ctx);
+
+ size_other = core_total - el3_size - el1_size;
+ printf("| %9u | %8luB ", i, el3_size);
+#if CTX_INCLUDE_EL2_REGS
+ size_other -= el2_size;
+ printf("| %8luB ", el2_size);
+#endif /* CTX_INCLUDE_EL2_REGS */
+ printf("| %8luB | %8luB | %8luB |\n", el1_size, size_other, core_total);
+
+ el3_total += el3_size;
+#if CTX_INCLUDE_EL2_REGS
+ el2_total += el2_size;
+#endif /* CTX_INCLUDE_EL2_REGS */
+ el1_total += el1_size;
+ other_total += size_other;
+ total += core_total;
+ }
+ PRINT_MEM_USAGE_SEPARATOR();
+ PRINT_MEM_USAGE_SEPARATOR();
+ printf("| All | %8luB ", el3_total);
+#if CTX_INCLUDE_EL2_REGS
+ printf("| %8luB ", el2_total);
+#endif /* CTX_INCLUDE_EL2_REGS */
+ printf("| %8luB | %8luB | %8luB |\n", el1_total, other_total, total);
+ PRINT_MEM_USAGE_SEPARATOR();
+ printf("\n");
+
+ /* Compute memory usage for the global context */
+ per_world_ctx_size = sizeof(per_world_context[security_state_idx]);
+
+ total += per_world_ctx_size;
+
+ printf("Per-world context: %luB\n\n", per_world_ctx_size);
+
+ printf("TOTAL: %luB\n", total);
+
+ return total;
+}
+
+/********************************************************************************
+ * Reports the allocated memory for every security state and then reports the
+ * total system-wide allocated memory.
+ *******************************************************************************/
+void report_ctx_memory_usage(void)
+{
+ INFO("Context memory allocation:\n");
+
+ size_t total = 0U;
+
+ for (unsigned int i = 0U; i < CPU_CONTEXT_NUM; i++) {
+ const char *context_name = get_context_name_by_idx(i);
+ size_t len = 0U;
+
+ printf("Memory usage for %s:\n", context_name);
+ total += report_allocated_memory(i);
+ printf("------------------------"
+#if CTX_INCLUDE_EL2_REGS
+ "------"
+#endif /* CTX_INCLUDE_EL2_REGS */
+ );
+ len = NAME_PLACEHOLDER_LEN - printf("End %s", context_name);
+ PRINT_DASH(len);
+ printf(
+#if CTX_INCLUDE_EL2_REGS
+ "------"
+#endif /* CTX_INCLUDE_EL2_REGS */
+ "-----------------------\n\n");
+ }
+
+ printf("Total context memory allocated: %luB\n\n", total);
+}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index ac9d44b..1802077 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -378,3 +378,6 @@
# Disable including MPAM EL2 registers in context by default since currently
# it's only enabled for NS world
CTX_INCLUDE_MPAM_REGS := 0
+
+# Enable context memory usage reporting during BL31 setup.
+PLATFORM_REPORT_CTX_MEM_USE := 0
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index a7fadf6..22ae9d3 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,17 +1,10 @@
/*
- * Copyright (c) 2021-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/* corstone1000 platform provides custom values for the macros defined in
- * arm_def.h , so only platform_def.h needs to be included
- */
-#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
-#include "plat/arm/common/arm_def.h"
-#else
-#include <platform_def.h>
-#endif
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
.global arm_rotpk_header
.section .rodata.arm_rotpk_hash, "a"
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 442d187..6953b89 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,15 +10,13 @@
#include <common/tbbr/tbbr_img_def.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/rotpk/rotpk_def.h>
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_spm_def.h>
#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
-#define ARM_ROTPK_HEADER_LEN 19
-#define ARM_ROTPK_HASH_LEN 32
-
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 65749f3..349233a 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -60,7 +60,9 @@
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+#endif
#define PLAT_NS_IMAGE_SIZE U(0x00200000)
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 97f4f24..6136820 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -153,6 +153,10 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
BL32_BASE ?= 0xbe000000
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index d5176dd..8e7be98 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -45,7 +45,9 @@
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+#endif
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index e0826e2..6036b6a 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -59,6 +59,10 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
BL32_BASE ?= 0xbe000000
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 1281270..4a03830 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -62,7 +62,9 @@
#define PLAT_SDEI_SGI_PRIVATE U(9)
/* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+#endif
#define PLAT_NS_IMAGE_SIZE U(0x00200000)
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index ce69071..40764b1 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -150,6 +150,10 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
BL32_BASE ?= 0x56000000
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 2526a02..b04f391 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -38,7 +38,9 @@
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* non-secure uboot base */
+#ifndef PLAT_NS_IMAGE_OFFSET
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+#endif
#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000)
/* GICv3 base address */
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index b1c189f..2356cbd 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -55,6 +55,10 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ifneq (${PRELOADED_BL33_BASE},)
+$(eval $(call add_define_val,PLAT_NS_IMAGE_OFFSET,${PRELOADED_BL33_BASE}))
+endif
+
BL32_BASE ?= 0xfe000000
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 0895bf9..9ef7598 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -9,6 +9,7 @@
#define PLAT_SOCFPGA_DEF_H
#include "agilex_system_manager.h"
+#include <lib/utils_def.h>
#include <platform_def.h>
/* Platform Setting */
@@ -90,8 +91,8 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
* SDMMC related pointer function
@@ -106,6 +107,6 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index 5c92f72..f81480d 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -53,6 +53,7 @@
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \
+ plat/intel/soc/common/drivers/ddr/ddr.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index f865124..391eac6 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -398,12 +398,21 @@
return mpu_clk;
}
+uint32_t get_l4_clk(void)
+{
+ uint32_t l4_clk;
+
+ l4_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
+ CLKMGR_PERPLL_PLLC1);
+ return l4_clk;
+}
+
/* Get cpu freq clock */
uint32_t get_cpu_clk(void)
{
uint32_t cpu_clk;
- cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
+ cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk;
}
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.c b/plat/intel/soc/common/drivers/ddr/ddr.c
index 188302f..62f03ef 100644
--- a/plat/intel/soc/common/drivers/ddr/ddr.c
+++ b/plat/intel/soc/common/drivers/ddr/ddr.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <errno.h>
#include <common/debug.h>
+#include <drivers/delay_timer.h>
#include "ddr.h"
#include <lib/mmio.h>
#include "socfpga_handoff.h"
@@ -340,3 +341,143 @@
NOTICE("DDR init successfully\n");
return status;
}
+
+int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
+{
+ uint32_t temp[9] = {0};
+ int ret = 0;
+
+ /* Write default value to prevent scrubber stop due to lower power */
+ mmio_write_32(0, umctl2_base + DDR4_PWRCTL_OFFSET);
+
+ /* To backup user configurations in temp array */
+ temp[0] = mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET);
+ temp[1] = mmio_read_32(umctl2_base + DDR4_SBRWDATA0_OFFSET);
+ temp[2] = mmio_read_32(umctl2_base + DDR4_SBRSTART0_OFFSET);
+ if (umctl2_type == DDR_TYPE_DDR4) {
+ temp[3] = mmio_read_32(umctl2_base + DDR4_SBRWDATA1_OFFSET);
+ temp[4] = mmio_read_32(umctl2_base + DDR4_SBRSTART1_OFFSET);
+ }
+ temp[5] = mmio_read_32(umctl2_base + DDR4_SBRRANGE0_OFFSET);
+ temp[6] = mmio_read_32(umctl2_base + DDR4_SBRRANGE1_OFFSET);
+ temp[7] = mmio_read_32(umctl2_base + DDR4_ECCCFG0_OFFSET);
+ temp[8] = mmio_read_32(umctl2_base + DDR4_ECCCFG1_OFFSET);
+
+ if (umctl2_type != DDR_TYPE_DDR4) {
+ /* Lock ECC region, ensure this regions is not being accessed */
+ mmio_setbits_32(umctl2_base + DDR4_ECCCFG1_OFFSET,
+ LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK);
+ }
+ /* Disable input traffic per port */
+ mmio_clrbits_32(umctl2_base + DDR4_PCTRL0_OFFSET, DDR4_PCTRL0_PORT_EN);
+ /* Disables scrubber */
+ mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+ /* Polling all scrub writes data have been sent */
+ ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+ DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
+
+ if (ret) {
+ INFO("%s: Timeout while waiting for", __func__);
+ INFO(" sending all scrub data\n");
+ return ret;
+ }
+
+ /* LPDDR4 supports inline ECC only */
+ if (umctl2_type != DDR_TYPE_DDR4) {
+ /*
+ * Setting all regions for protected, this is required for
+ * srubber to init whole LPDDR4 expect ECC region
+ */
+ mmio_write_32(((ONE_EIGHT <<
+ LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT) |
+ (ALL_PROTECTED << LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT)),
+ umctl2_base + DDR4_ECCCFG0_OFFSET);
+ }
+
+ /* Scrub_burst = 1, scrub_mode = 1(performs writes) */
+ mmio_write_32(DDR4_SBRCTL_SCRUB_BURST_1 | DDR4_SBRCTL_SCRUB_WRITE,
+ umctl2_base + DDR4_SBRCTL_OFFSET);
+
+ /* Wipe DDR content after calibration */
+ ret = ddr_zerofill_scrubber(umctl2_base, umctl2_type);
+ if (ret) {
+ ERROR("Failed to clear DDR content\n");
+ }
+
+ /* Polling all scrub writes data have been sent */
+ ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+ DDR4_SBRSTAT_SCRUB_BUSY, true, 5000);
+ if (ret) {
+ INFO("%s: Timeout while waiting for", __func__);
+ INFO(" sending all scrub data\n");
+ return ret;
+ }
+
+ /* Disables scrubber */
+ mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+
+ /* Restore user configurations */
+ mmio_write_32(temp[0], umctl2_base + DDR4_SBRCTL_OFFSET);
+ mmio_write_32(temp[1], umctl2_base + DDR4_SBRWDATA0_OFFSET);
+ mmio_write_32(temp[2], umctl2_base + DDR4_SBRSTART0_OFFSET);
+ if (umctl2_type == DDR_TYPE_DDR4) {
+ mmio_write_32(temp[3], umctl2_base + DDR4_SBRWDATA1_OFFSET);
+ mmio_write_32(temp[4], umctl2_base + DDR4_SBRSTART1_OFFSET);
+ }
+ mmio_write_32(temp[5], umctl2_base + DDR4_SBRRANGE0_OFFSET);
+ mmio_write_32(temp[6], umctl2_base + DDR4_SBRRANGE1_OFFSET);
+ mmio_write_32(temp[7], umctl2_base + DDR4_ECCCFG0_OFFSET);
+ mmio_write_32(temp[8], umctl2_base + DDR4_ECCCFG1_OFFSET);
+
+ /* Enables ECC scrub on scrubber */
+ if (!(mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET) & DDR4_SBRCTL_SCRUB_WRITE)) {
+ /* Enables scrubber */
+ mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+ }
+
+ return 0;
+}
+
+int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)
+{
+ int ret = 0;
+
+ /* Zeroing whole DDR */
+ mmio_write_32(0, umctl2_base + DDR4_SBRWDATA0_OFFSET);
+ mmio_write_32(0, umctl2_base + DDR4_SBRSTART0_OFFSET);
+ if (umctl2_type == DDR_TYPE_DDR4) {
+ mmio_write_32(0, umctl2_base + DDR4_SBRWDATA1_OFFSET);
+ mmio_write_32(0, umctl2_base + DDR4_SBRSTART1_OFFSET);
+ }
+ mmio_write_32(0, umctl2_base + DDR4_SBRRANGE0_OFFSET);
+ mmio_write_32(0, umctl2_base + DDR4_SBRRANGE1_OFFSET);
+
+ NOTICE("Enabling scrubber (zeroing whole DDR) ...\n");
+
+ /* Enables scrubber */
+ mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);
+ /* Polling all scrub writes commands have been sent */
+ ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),
+ DDR4_SBRSTAT_SCRUB_DONE, true, 5000);
+ if (ret) {
+ INFO("%s: Timeout while waiting for", __func__);
+ INFO(" sending all scrub commands\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
+{
+ int time_out = delay_ms;
+
+ while (time_out-- > 0) {
+
+ if ((mmio_read_32(addr) & mask) == match) {
+ return 0;
+ }
+ udelay(1000);
+ }
+ return -ETIMEDOUT;
+}
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.h b/plat/intel/soc/common/drivers/ddr/ddr.h
index 416b64e..e50cda8 100644
--- a/plat/intel/soc/common/drivers/ddr/ddr.h
+++ b/plat/intel/soc/common/drivers/ddr/ddr.h
@@ -10,6 +10,28 @@
#include <lib/mmio.h>
#include "socfpga_handoff.h"
+enum ddr_type {
+ DDR_TYPE_LPDDR4_0,
+ DDR_TYPE_LPDDR4_1,
+ DDR_TYPE_DDR4,
+ DDR_TYPE_LPDDR5_0,
+ DDR_TYPE_LPDDR5_1,
+ DDR_TYPE_DDR5,
+ DDR_TYPE_UNKNOWN
+};
+
+/* Region size for ECCCFG0.ecc_region_map */
+enum region_size {
+ ONE_EIGHT,
+ ONE_SIXTEENTH,
+ ONE_THIRTY_SECOND,
+ ONE_SIXTY_FOURTH
+};
+
+/* DATATYPE DEFINATION */
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
/* MACRO DEFINATION */
#define IO96B_0_REG_BASE 0x18400000
#define IO96B_1_REG_BASE 0x18800000
@@ -86,6 +108,34 @@
#define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data)
+/* DDR4 Register */
+#define DDR4_PWRCTL_OFFSET 0x30
+#define DDR4_SBRCTL_OFFSET 0x0F24
+#define DDR4_SBRSTAT_OFFSET 0x0F28
+#define DDR4_SBRWDATA0_OFFSET 0x0F2C
+#define DDR4_SBRSTART0_OFFSET 0x0F38
+#define DDR4_SBRWDATA1_OFFSET 0x0F30
+#define DDR4_SBRSTART1_OFFSET 0x0F3C
+#define DDR4_SBRRANGE0_OFFSET 0x0F40
+#define DDR4_SBRRANGE1_OFFSET 0x0F44
+#define DDR4_ECCCFG0_OFFSET 0x70
+#define DDR4_ECCCFG1_OFFSET 0x74
+#define DDR4_PCTRL0_OFFSET 0x0490
+
+#define LPDDR4_ECCCFG0_ECC_REGION_MAP_GRANU_SHIFT 30
+#define ALL_PROTECTED 0x7F
+#define LPDDR4_ECCCFG0_ECC_REGION_MAP_SHIFT 8
+
+
+
+#define LPDDR4_ECCCFG1_ECC_REGIONS_PARITY_LOCK BIT(4)
+#define DDR4_PCTRL0_PORT_EN BIT(0)
+#define DDR4_SBRCTL_SCRUB_EN BIT(0)
+#define DDR4_SBRSTAT_SCRUB_BUSY BIT(0)
+#define DDR4_SBRCTL_SCRUB_BURST_1 BIT(4)
+#define DDR4_SBRCTL_SCRUB_WRITE BIT(2)
+#define DDR4_SBRSTAT_SCRUB_DONE BIT(1)
+
/* FUNCTION DEFINATION */
int ddr_calibration_check(void);
@@ -109,4 +159,10 @@
bool is_ddr_init_in_progress(void);
+int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
+
+int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type);
+
+int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms);
+
#endif
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 843ec69..adeb069 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -2175,14 +2175,28 @@
param_addr_ptr = (uint64_t *) param_addr;
- /*
- * Since crypto param size vary between mode.
- * Check ECB here and limit to size 12 bytes
- */
- if (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_ECB_MODE) &&
- (param_size > FCS_CRYPTO_ECB_BUFFER_SIZE)) {
+ /* Check if mbox_error is not NULL or 0xF or 0x3FF */
+ if (mbox_error == NULL || *mbox_error > 0xF ||
+ (*mbox_error != 0 && *mbox_error != 0x3FF)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+
+ /* Check if param_addr is not 0 or larger that 0xFFFFFFFFFF */
+ if (param_addr == 0 || param_addr > 0xFFFFFFFFFF) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ /*
+ * Check if not ECB, CBC and CTR mode, addr ptr is NULL.
+ * Return "Reject" status
+ */
+ if ((param_addr_ptr == NULL) ||
+ (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE))) {
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
/*
* Since crypto param size vary between mode.
* Check CBC/CTR here and limit to size 28 bytes
@@ -2193,7 +2207,12 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if (mbox_error == NULL) {
+ /*
+ * Since crypto param size vary between mode.
+ * Check ECB here and limit to size 12 bytes
+ */
+ if (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_ECB_MODE) &&
+ (param_size > FCS_CRYPTO_ECB_BUFFER_SIZE)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 7aa6b70..5204146 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -431,7 +431,7 @@
* To request handshake
* Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
*/
- INFO("Set S2F hdskreq ...\n");
+ VERBOSE("Set S2F hdskreq ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_SOC2FPGAREQ);
@@ -451,7 +451,7 @@
* To clear idle request
* Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
*/
- INFO("Clear S2F hdskreq ...\n");
+ VERBOSE("Clear S2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_SOC2FPGAREQ);
@@ -459,7 +459,7 @@
* To assert reset
* Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
*/
- INFO("Assert S2F ...\n");
+ VERBOSE("Assert S2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
@@ -472,7 +472,7 @@
* To deassert reset
* Write Reset Manager brgmodrst[soc2fpga] = 0
*/
- INFO("Deassert S2F ...\n");
+ VERBOSE("Deassert S2F ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
}
@@ -483,7 +483,7 @@
* To request handshake
* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
*/
- INFO("Set LWS2F hdskreq ...\n");
+ VERBOSE("Set LWS2F hdskreq ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
@@ -503,7 +503,7 @@
* To clear idle request
* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
*/
- INFO("Clear LWS2F hdskreq ...\n");
+ VERBOSE("Clear LWS2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
@@ -511,7 +511,7 @@
* To assert reset
* Write Reset Manager brgmodrst[lwsoc2fpga] = 1
*/
- INFO("Assert LWS2F ...\n");
+ VERBOSE("Assert LWS2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
@@ -524,7 +524,7 @@
* To deassert reset
* Write Reset Manager brgmodrst[lwsoc2fpga] = 0
*/
- INFO("Deassert LWS2F ...\n");
+ VERBOSE("Deassert LWS2F ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
}
@@ -557,21 +557,21 @@
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
*/
- INFO("Set FPGA hdsken(fpgahsen) ...\n");
+ VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
/*
* To request handshake
* Write Reset Manager hdskreq[fpgahsreq] = 1
*/
- INFO("Set FPGA hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 1
*/
- INFO("Get FPGA hdskack(fpgahsack) ...\n");
+ VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
300);
@@ -584,7 +584,7 @@
* To fence and drain traffic
* Write Reset Manager hdskreq[f2s_flush_req] = 1
*/
- INFO("Set F2S hdskreq(f2s_flush_req) ...\n");
+ VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
@@ -592,7 +592,7 @@
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 1
*/
- INFO("Get F2S hdskack(f2s_flush_ack) ...\n");
+ VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
300);
@@ -605,14 +605,14 @@
* To clear idle request
* Write Reset Manager hdskreq[fpgahsreq] = 1
*/
- INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To clear idle request
* Write Reset Manager hdskreq[f2s_flush_req] = 1
*/
- INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
+ VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
@@ -620,7 +620,7 @@
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 0
*/
- INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
300);
@@ -633,7 +633,7 @@
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 0
*/
- INFO("Get FPGA hdskack(fpgahsack) ...\n");
+ VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -646,7 +646,7 @@
* To assert reset
* Write Reset Manager brgmodrst[fpga2soc] = 1
*/
- INFO("Assert F2S ...\n");
+ VERBOSE("Assert F2S ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
/* ToDo: Shall use udelay for product release */
@@ -658,11 +658,11 @@
* To deassert reset
* Write Reset Manager brgmodrst[fpga2soc] = 0
*/
- INFO("Deassert F2S ...\n");
+ VERBOSE("Deassert F2S ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
- INFO("Deassert F2S f2soc_enable ...\n");
+ VERBOSE("Deassert F2S f2soc_enable ...\n");
mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
SYSMGR_F2S_BRIDGE_CTRL_EN);
}
@@ -673,21 +673,21 @@
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
*/
- INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
+ VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
/*
* To request handshake
* Write Reset Manager hdskreq[fpgahsreq] = 1
*/
- INFO("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 1
*/
- INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
300);
@@ -700,7 +700,7 @@
* To fence and drain traffic
* Write Reset Manager hdskreq[f2sdram_flush_req] = 1
*/
- INFO("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ VERBOSE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_F2SDRAM0REQ);
@@ -708,7 +708,7 @@
* To poll idle status
* Read Reset Manager hdskack[f2sdram_flush_ack] = 1
*/
- INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
300);
@@ -721,21 +721,21 @@
* To clear idle request
* Write Reset Manager hdskreq[fpgahsreq] = 1
*/
- INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To clear idle request
* Write Reset Manager hdskreq[f2sdram_flush_req] = 1
*/
- INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
/*
* To poll idle status
* Read Reset Manager hdskack[f2sdram_flush_ack] = 0
*/
- INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
300);
@@ -748,7 +748,7 @@
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 0
*/
- INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -761,7 +761,7 @@
* To assert reset
* Write Reset Manager brgmodrst[fpga2sdram] = 1
*/
- INFO("Assert F2SDRAM ...\n");
+ VERBOSE("Assert F2SDRAM ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
@@ -774,7 +774,7 @@
* To deassert reset
* Write Reset Manager brgmodrst[fpga2sdram] = 0
*/
- INFO("Deassert F2SDRAM ...\n");
+ VERBOSE("Deassert F2SDRAM ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
@@ -782,7 +782,7 @@
* Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
* f2s_ready_latency_enable
*/
- INFO("Clear F2SDRAM f2s_ready_latency_enable ...\n");
+ VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
FLAGOUTCLR0_F2SDRAM0_ENABLE);
}
@@ -885,7 +885,7 @@
* To clear handshake
* Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
*/
- INFO("Set S2F hdskreq ...\n");
+ VERBOSE("Set S2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_SOC2FPGAREQ);
@@ -905,7 +905,7 @@
* To assert reset
* Write Reset Manager brgmodrst[soc2fpga] = 1
*/
- INFO("Assert S2F ...\n");
+ VERBOSE("Assert S2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_SOC2FPGA);
@@ -921,7 +921,7 @@
* To clear handshake
* Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
*/
- INFO("Set LWS2F hdskreq ...\n");
+ VERBOSE("Set LWS2F hdskreq ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
@@ -941,7 +941,7 @@
* To assert reset
* Write Reset Manager brgmodrst[lwsoc2fpga] = 1
*/
- INFO("Assert LWS2F ...\n");
+ VERBOSE("Assert LWS2F ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_LWHPS2FPGA);
@@ -986,21 +986,21 @@
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
*/
- INFO("Set FPGA hdsken(fpgahsen) ...\n");
+ VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
/*
* To clear handshake request
* Write Reset Manager hdskreq[fpgahsreq] = 0
*/
- INFO("Clear FPGA hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To clear handshake request
* Write Reset Manager hdskreq[f2s_flush_req] = 0
*/
- INFO("Clear F2S hdskreq(f2s_flush_req) ...\n");
+ VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
RSTMGR_HDSKREQ_FPGA2SOCREQ);
@@ -1008,7 +1008,7 @@
* To poll idle status
* Read Reset Manager hdskack[f2s_flush_ack] = 0
*/
- INFO("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
300);
@@ -1021,7 +1021,7 @@
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 0
*/
- INFO("Get FPGA hdskack(fpgahsack) ...\n");
+ VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -1034,7 +1034,7 @@
* To assert reset
* Write Reset Manager brgmodrst[fpga2soc] = 1
*/
- INFO("Assert F2S ...\n");
+ VERBOSE("Assert F2S ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
/* ToDo: Shall use udelay for product release */
@@ -1043,7 +1043,7 @@
}
/* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
- INFO("Assert F2S f2soc_enable ...\n");
+ VERBOSE("Assert F2S f2soc_enable ...\n");
mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
SYSMGR_F2S_BRIDGE_CTRL_EN);
}
@@ -1054,28 +1054,28 @@
* To request handshake
* Write Reset Manager hdsken[fpgahsen] = 1
*/
- INFO("Set F2SDRAM hdsken(fpgahsen) ...\n");
+ VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
/*
* To clear handshake request
* Write Reset Manager hdskreq[fpgahsreq] = 0
*/
- INFO("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
+ VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
/*
* To clear handshake request
* Write Reset Manager hdskreq[f2sdram_flush_req] = 0
*/
- INFO("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
+ VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
/*
* To poll idle status
* Read Reset Manager hdskack[f2sdram_flush_ack] = 0
*/
- INFO("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
300);
@@ -1088,7 +1088,7 @@
* To poll idle status
* Read Reset Manager hdskack[fpgahsack] = 0
*/
- INFO("Get F2SDRAM hdskack(fpgahsack) ...\n");
+ VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
ret = poll_idle_status_by_counter(SOCFPGA_RSTMGR(HDSKACK),
RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
300);
@@ -1101,7 +1101,7 @@
* To assert reset
* Write Reset Manager brgmodrst[fpga2sdram] = 1
*/
- INFO("Assert F2SDRAM ...\n");
+ VERBOSE("Assert F2SDRAM ...\n");
mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
@@ -1114,7 +1114,7 @@
* Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
* f2s_ready_latency_enable
*/
- INFO("Assert F2SDRAM f2s_ready_latency_enable ...\n");
+ VERBOSE("Assert F2SDRAM f2s_ready_latency_enable ...\n");
mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
FLAGOUTCLR0_F2SDRAM0_ENABLE);
}
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 3568e3b..1eafeef 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -9,14 +9,15 @@
#define PLAT_SOCFPGA_DEF_H
#include <platform_def.h>
+#include <lib/utils_def.h>
#include "n5x_system_manager.h"
/* Platform Setting */
-#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
-#define PLAT_PRIMARY_CPU 0
+#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
-#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -34,10 +35,10 @@
#define SOCFPGA_SYSMGR_REG_BASE U(0xffd12000)
#define SOCFPGA_ECC_QSPI_REG_BASE U(0xffa22000)
-#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
-#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
-#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
-#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
+#define SOCFPGA_L4_PER_SCR_REG_BASE U(0xffd21000)
+#define SOCFPGA_L4_SYS_SCR_REG_BASE U(0xffd21100)
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE U(0xffd21200)
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE U(0xffd21300)
/*******************************************************************************
@@ -64,17 +65,17 @@
#define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000)
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe1b000)
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe1b000)
-#define BL31_BASE (0x1000)
-#define BL31_LIMIT (0x81000)
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
/*******************************************************************************
* UART related constants
******************************************************************************/
-#define PLAT_UART0_BASE (0xFFC02000)
-#define PLAT_UART1_BASE (0xFFC02100)
+#define PLAT_UART0_BASE (0xFFC02000)
+#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
@@ -84,19 +85,19 @@
/*******************************************************************************
* GIC related constants
******************************************************************************/
-#define PLAT_GIC_BASE (0xFFFC0000)
-#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE 0
+#define PLAT_GIC_BASE (0xFFFC0000)
+#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE 0
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
-#define SDMMC_READ_BLOCKS mmc_read_blocks
-#define SDMMC_WRITE_BLOCKS mmc_write_blocks
+#define SDMMC_READ_BLOCKS mmc_read_blocks
+#define SDMMC_WRITE_BLOCKS mmc_write_blocks
/*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@@ -105,6 +106,6 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/n5x/soc/n5x_clock_manager.c b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
index 2e3acc9..c33140d 100644
--- a/plat/intel/soc/n5x/soc/n5x_clock_manager.c
+++ b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
@@ -150,7 +150,7 @@
{
uint32_t cpu_clk = 0;
- cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
+ cpu_clk = get_l4_clk()/PLAT_HZ_CONVERT_TO_MHZ;
return cpu_clk;
}
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h
index 790dbc1..c7632be 100644
--- a/plat/intel/soc/stratix10/include/s10_clock_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h
@@ -95,6 +95,7 @@
uint32_t get_uart_clk(void);
uint32_t get_mmc_clk(void);
uint32_t get_l3_clk(uint32_t ref_clk);
+uint32_t get_cpu_clk(void);
uint32_t get_ref_clk(uint32_t pllglob);
uint32_t get_mpu_periph_clk(void);
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 84b7eec..7f452bd 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -8,14 +8,15 @@
#define PLAT_SOCFPGA_DEF_H
#include <platform_def.h>
+#include <lib/utils_def.h>
#include "s10_system_manager.h"
/* Platform Setting */
-#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
-#define PLAT_PRIMARY_CPU 0
+#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
-#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
@@ -64,17 +65,17 @@
#define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000)
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe2b000)
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe2b000)
-#define BL31_BASE (0x1000)
-#define BL31_LIMIT (0x81000)
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
/*******************************************************************************
* UART related constants
******************************************************************************/
-#define PLAT_UART0_BASE (0xFFC02000)
-#define PLAT_UART1_BASE (0xFFC02100)
+#define PLAT_UART0_BASE (0xFFC02000)
+#define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
@@ -84,19 +85,19 @@
/*******************************************************************************
* GIC related constants
******************************************************************************/
-#define PLAT_GIC_BASE (0xFFFC0000)
-#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE 0
+#define PLAT_GIC_BASE (0xFFFC0000)
+#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE 0
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
-#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
* SDMMC related pointer function
******************************************************************************/
-#define SDMMC_READ_BLOCKS mmc_read_blocks
-#define SDMMC_WRITE_BLOCKS mmc_write_blocks
+#define SDMMC_READ_BLOCKS mmc_read_blocks
+#define SDMMC_WRITE_BLOCKS mmc_write_blocks
/*******************************************************************************
* sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset
@@ -105,7 +106,7 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400)
#endif /* PLATSOCFPGA_DEF_H */
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 6bc96fb..9567c45 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -53,6 +53,7 @@
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
+ plat/intel/soc/common/drivers/ddr/ddr.c \
plat/intel/soc/common/drivers/wdt/watchdog.c
include lib/zlib/zlib.mk
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index 2dcac69..36d9f5b 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -126,6 +126,11 @@
ENABLE_SME_FOR_NS := 2
endif
+ifeq (${ENABLE_RME},1)
+BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
+ plat/qemu/common/qemu_realm_attest_key.c
+endif
+
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
diff --git a/plat/qemu/common/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c
index bb1797d..c444be4 100644
--- a/plat/qemu/common/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,11 +67,28 @@
# ifdef QEMU_LOAD_BL32
.next_handoff_image_id = BL32_IMAGE_ID,
+# elif ENABLE_RME
+ .next_handoff_image_id = RMM_IMAGE_ID,
# else
.next_handoff_image_id = BL33_IMAGE_ID,
# endif
},
#endif /* __aarch64__ */
+
+#if ENABLE_RME
+ /* Fill RMM related information */
+ { .image_id = RMM_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE),
+ .ep_info.pc = RMM_BASE,
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = RMM_BASE,
+ .image_info.image_max_size = RMM_LIMIT - RMM_BASE,
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+#endif /* ENABLE_RME */
+
# ifdef QEMU_LOAD_BL32
#ifdef __aarch64__
@@ -95,7 +112,11 @@
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+#if ENABLE_RME
+ .next_handoff_image_id = RMM_IMAGE_ID,
+#else
.next_handoff_image_id = BL33_IMAGE_ID,
+#endif
},
/*
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 231f23a..8c7518d 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <platform_def.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -23,30 +24,33 @@
#endif
#include <lib/utils.h>
#include <plat/common/platform.h>
+#if ENABLE_RME
+#include <qemu_pas_def.h>
+#endif
#include "qemu_private.h"
#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
bl2_tzram_layout.total_base, \
bl2_tzram_layout.total_size, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_BL2_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END - BL_CODE_BASE, \
- MT_CODE | MT_SECURE), \
+ MT_CODE | EL3_PAS), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
- MT_RO_DATA | MT_SECURE)
+ MT_RO_DATA | EL3_PAS)
#if USE_COHERENT_MEM
#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL2 */
@@ -101,6 +105,18 @@
return;
}
+#if ENABLE_RME
+ if (fdt_add_reserved_memory(fdt, "rmm", REALM_DRAM_BASE,
+ REALM_DRAM_SIZE)) {
+ ERROR("Failed to reserve RMM memory in Device Tree\n");
+ return;
+ }
+
+ INFO("Reserved RMM memory [0x%lx, 0x%lx] in Device tree\n",
+ (uintptr_t)REALM_DRAM_BASE,
+ (uintptr_t)REALM_DRAM_BASE + REALM_DRAM_SIZE - 1);
+#endif
+
ret = fdt_pack(fdt);
if (ret < 0)
ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
@@ -138,6 +154,53 @@
#endif
}
+#if ENABLE_RME
+static void bl2_plat_gpt_setup(void)
+{
+ /*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+ pas_region_t pas_regions[] = {
+ QEMU_PAS_ROOT,
+ QEMU_PAS_SECURE,
+ QEMU_PAS_GPTS,
+ QEMU_PAS_NS0,
+ QEMU_PAS_REALM,
+ QEMU_PAS_NS1,
+ };
+
+ /*
+ * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry
+ * covering 1GB (currently the only supported option), then covering
+ * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the
+ * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
+ */
+ if (gpt_init_l0_tables(GPCCR_PPS_1TB, PLAT_QEMU_L0_GPT_BASE,
+ PLAT_QEMU_L0_GPT_SIZE) < 0) {
+ ERROR("gpt_init_l0_tables() failed!\n");
+ panic();
+ }
+
+ /* Carve out defined PAS ranges. */
+ if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
+ PLAT_QEMU_L1_GPT_BASE,
+ PLAT_QEMU_L1_GPT_SIZE,
+ pas_regions,
+ (unsigned int)(sizeof(pas_regions) /
+ sizeof(pas_region_t))) < 0) {
+ ERROR("gpt_init_pas_l1_tables() failed!\n");
+ panic();
+ }
+
+ INFO("Enabling Granule Protection Checks\n");
+ if (gpt_enable() < 0) {
+ ERROR("gpt_enable() failed!\n");
+ panic();
+ }
+}
+#endif
+
void bl2_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
@@ -146,16 +209,31 @@
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
+#if ENABLE_RME
+ MAP_RMM_DRAM,
+ MAP_GPT_L0_REGION,
+ MAP_GPT_L1_REGION,
+#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
+#if ENABLE_RME
+ /* BL2 runs in EL3 when RME enabled. */
+ assert(get_armv9_2_feat_rme_support() != 0U);
+ enable_mmu_el3(0);
+
+ /* Initialise and enable granule protection after MMU. */
+ bl2_plat_gpt_setup();
+#else /* ENABLE_RME */
+
#ifdef __aarch64__
enable_mmu_el1(0);
#else
enable_mmu_svc_mon(0);
#endif
+#endif /* ENABLE_RME */
}
/*******************************************************************************
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index f309efd..894b842 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <common/bl_common.h>
#include <drivers/arm/pl061_gpio.h>
+#include <lib/gpt_rme/gpt_rme.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
@@ -40,6 +41,9 @@
*/
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+#if ENABLE_RME
+static entry_point_info_t rmm_image_ep_info;
+#endif
/*******************************************************************************
* Perform any BL3-1 early platform setup. Here is an opportunity to copy
@@ -72,13 +76,18 @@
bl_params_node_t *bl_params = params_from_bl2->head;
/*
- * Copy BL33 and BL32 (if present), entry point information.
+ * Copy BL33, BL32 and RMM (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
while (bl_params) {
if (bl_params->image_id == BL32_IMAGE_ID)
bl32_image_ep_info = *bl_params->ep_info;
+#if ENABLE_RME
+ if (bl_params->image_id == RMM_IMAGE_ID)
+ rmm_image_ep_info = *bl_params->ep_info;
+#endif
+
if (bl_params->image_id == BL33_IMAGE_ID)
bl33_image_ep_info = *bl_params->ep_info;
@@ -87,6 +96,10 @@
if (!bl33_image_ep_info.pc)
panic();
+#if ENABLE_RME
+ if (!rmm_image_ep_info.pc)
+ panic();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -97,12 +110,31 @@
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
+#if ENABLE_RME
+ MAP_GPT_L0_REGION,
+ MAP_GPT_L1_REGION,
+ MAP_RMM_SHARED_MEM,
+#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
enable_mmu_el3(0);
+
+#if ENABLE_RME
+ /*
+ * Initialise Granule Protection library and enable GPC for the primary
+ * processor. The tables have already been initialized by a previous BL
+ * stage, so there is no need to provide any PAS here. This function
+ * sets up pointers to those tables.
+ */
+ if (gpt_runtime_init() < 0) {
+ ERROR("gpt_runtime_init() failed!\n");
+ panic();
+ }
+#endif /* ENABLE_RME */
+
}
static void qemu_gpio_init(void)
@@ -135,8 +167,18 @@
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
- next_image_info = (type == NON_SECURE)
- ? &bl33_image_ep_info : &bl32_image_ep_info;
+ if (type == NON_SECURE) {
+ next_image_info = &bl33_image_ep_info;
+ }
+#if ENABLE_RME
+ else if (type == REALM) {
+ next_image_info = &rmm_image_ep_info;
+ }
+#endif
+ else {
+ next_image_info = &bl32_image_ep_info;
+ }
+
/*
* None of the images on the ARM development platforms can have 0x0
* as the entrypoint
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index d4488a4..cafee6f 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,45 +11,48 @@
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <services/el3_spmc_ffa_memory.h>
+#if ENABLE_RME
+#include <services/rmm_core_manifest.h>
+#endif
#include <plat/common/platform.h>
#include "qemu_private.h"
#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
DEVICE0_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#ifdef DEVICE1_BASE
#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
DEVICE1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
#ifdef DEVICE2_BASE
#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
DEVICE2_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
SHARED_RAM_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
+ MT_MEMORY | MT_RO | EL3_PAS)
#define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
+ MT_MEMORY | MT_RO | EL3_PAS)
#ifdef FW_HANDOFF_BASE
#define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#endif
#ifdef FW_NS_HANDOFF_BASE
#define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \
@@ -138,6 +141,19 @@
};
#endif
+#ifdef IMAGE_RMM
+const mmap_region_t plat_qemu_mmap[] = {
+ MAP_DEVICE0,
+#ifdef MAP_DEVICE1
+ MAP_DEVICE1,
+#endif
+#ifdef MAP_DEVICE2
+ MAP_DEVICE2,
+#endif
+ {0}
+};
+#endif
+
/*******************************************************************************
* Returns QEMU platform specific memory map regions.
******************************************************************************/
@@ -190,3 +206,76 @@
return -1;
}
#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
+
+#if ENABLE_RME
+/*
+ * Get a pointer to the RMM-EL3 Shared buffer and return it
+ * through the pointer passed as parameter.
+ *
+ * This function returns the size of the shared buffer.
+ */
+size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
+{
+ *shared = (uintptr_t)RMM_SHARED_BASE;
+
+ return (size_t)RMM_SHARED_SIZE;
+}
+
+int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
+{
+ uint64_t checksum;
+ uintptr_t base;
+ uint64_t size;
+ struct ns_dram_bank *bank_ptr;
+
+ assert(manifest != NULL);
+
+ manifest->version = RMMD_MANIFEST_VERSION;
+ manifest->padding = 0U; /* RES0 */
+ manifest->plat_data = (uintptr_t)NULL;
+ manifest->plat_dram.num_banks = 1;
+
+ /*
+ * Array ns_dram_banks[] follows ns_dram_info structure:
+ *
+ * +-----------------------------------+
+ * | offset | field | comment |
+ * +----------+-----------+------------+
+ * | 0 | version | 0x00000002 |
+ * +----------+-----------+------------+
+ * | 4 | padding | 0x00000000 |
+ * +----------+-----------+------------+
+ * | 8 | plat_data | NULL |
+ * +----------+-----------+------------+
+ * | 16 | num_banks | |
+ * +----------+-----------+ |
+ * | 24 | banks | plat_dram |
+ * +----------+-----------+ |
+ * | 32 | checksum | |
+ * +----------+-----------+------------+
+ * | 40 | base 0 | |
+ * +----------+-----------+ bank[0] |
+ * | 48 | size 0 | |
+ * +----------+-----------+------------+
+ */
+ bank_ptr = (struct ns_dram_bank *)
+ ((uintptr_t)&manifest->plat_dram.checksum +
+ sizeof(manifest->plat_dram.checksum));
+
+ manifest->plat_dram.banks = bank_ptr;
+
+ /* Calculate checksum of plat_dram structure */
+ checksum = 1 + (uint64_t)bank_ptr;
+
+ base = NS_DRAM0_BASE;
+ size = NS_DRAM0_SIZE;
+ bank_ptr[0].base = base;
+ bank_ptr[0].size = size;
+ checksum += base + size;
+
+ /* Checksum must be 0 */
+ manifest->plat_dram.checksum = ~checksum + 1UL;
+
+ return 0;
+}
+#endif /* ENABLE_RME */
diff --git a/plat/qemu/common/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c
index 4c61b14..59bba86 100644
--- a/plat/qemu/common/qemu_io_storage.c
+++ b/plat/qemu/common/qemu_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,6 +33,7 @@
#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin"
#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin"
#define BL33_IMAGE_NAME "bl33.bin"
+#define RMM_IMAGE_NAME "rmm.bin"
#if TRUSTED_BOARD_BOOT
#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt"
@@ -96,6 +97,10 @@
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
+static const io_uuid_spec_t rmm_uuid_spec = {
+ .uuid = UUID_REALM_MONITOR_MGMT_FIRMWARE,
+};
+
#if TRUSTED_BOARD_BOOT
static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FW_CERT,
@@ -163,6 +168,10 @@
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
},
+ [RMM_IMAGE_ID] = {
+ .path = RMM_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
.path = TRUSTED_BOOT_FW_CERT_NAME,
@@ -289,6 +298,12 @@
(uintptr_t)&bl33_uuid_spec,
open_fip
},
+ [RMM_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&rmm_uuid_spec,
+ open_fip
+ },
+
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
new file mode 100644
index 0000000..cf3376d
--- /dev/null
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_platform_token[] = {
+ 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
+ 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
+ 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
+ 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
+ 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
+ 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
+ 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
+ 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
+ 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
+ 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
+ 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
+ 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
+ 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
+ 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
+ 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
+ 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
+ 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
+ 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
+ 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
+ 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
+ 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
+ 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
+ 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
+ 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
+ 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
+ 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
+ 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
+ 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
+ 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
+ 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
+ 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
+ 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
+ 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
+ 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
+ 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
+ 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
+ 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
+ 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
+ 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
+ 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
+ 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
+ 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
+ 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
+ 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
+};
+
+/*
+ * Get the hardcoded platform attestation token as QEMU does not support
+ * RSS.
+ */
+int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ (void)hash;
+ (void)hash_size;
+
+ if (*len < sizeof(sample_platform_token)) {
+ return -EINVAL;
+ }
+
+ (void)memcpy((void *)buf, (const void *)sample_platform_token,
+ sizeof(sample_platform_token));
+ *len = sizeof(sample_platform_token);
+
+ return 0;
+}
diff --git a/plat/qemu/common/qemu_realm_attest_key.c b/plat/qemu/common/qemu_realm_attest_key.c
new file mode 100644
index 0000000..abd569b
--- /dev/null
+++ b/plat/qemu/common/qemu_realm_attest_key.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_delegated_key[] = {
+ 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E,
+ 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6,
+ 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E,
+ 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7,
+ 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68
+};
+
+/*
+ * Get the hardcoded delegated realm attestation key as QEMU
+ * does not support RSS.
+ */
+int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
+ unsigned int type)
+{
+ if (*len < sizeof(sample_delegated_key)) {
+ return -EINVAL;
+ }
+
+ (void)memcpy((void *)buf, (const void *)sample_delegated_key,
+ sizeof(sample_delegated_key));
+ *len = sizeof(sample_delegated_key);
+
+ return 0;
+}
diff --git a/plat/qemu/common/trp/qemu_trp_setup.c b/plat/qemu/common/trp/qemu_trp_setup.c
new file mode 100644
index 0000000..0b914ee
--- /dev/null
+++ b/plat/qemu/common/trp/qemu_trp_setup.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <platform_def.h>
+#include <services/rmm_core_manifest.h>
+#include <services/rmmd_svc.h>
+#include <services/trp/platform_trp.h>
+#include <trp_helpers.h>
+
+#include "../qemu_private.h"
+
+/*******************************************************************************
+ * Received from boot manifest and populated here
+ ******************************************************************************/
+extern uint32_t trp_boot_manifest_version;
+
+static int qemu_trp_process_manifest(struct rmm_manifest *manifest)
+{
+ /* padding field on the manifest must be RES0 */
+ assert(manifest->padding == 0U);
+
+ /* Verify the Boot Manifest Version. Only the Major is considered */
+ if (RMMD_MANIFEST_VERSION_MAJOR !=
+ RMMD_GET_MANIFEST_VERSION_MAJOR(manifest->version)) {
+ return E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED;
+ }
+
+ trp_boot_manifest_version = manifest->version;
+ flush_dcache_range((uintptr_t)manifest, sizeof(struct rmm_manifest));
+
+ return 0;
+}
+
+void trp_early_platform_setup(struct rmm_manifest *manifest)
+{
+ int rc;
+
+ rc = qemu_trp_process_manifest(manifest);
+ if (rc != 0) {
+ trp_boot_abort(rc);
+ }
+
+ qemu_console_init();
+}
diff --git a/plat/qemu/common/trp/trp-qemu-common.mk b/plat/qemu/common/trp/trp-qemu-common.mk
new file mode 100644
index 0000000..081ba55
--- /dev/null
+++ b/plat/qemu/common/trp/trp-qemu-common.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# TRP source files common to QEMU platforms
+RMM_SOURCES += plat/qemu/common/trp/qemu_trp_setup.c \
+ plat/common/aarch64/platform_mp_stack.S \
+ plat/qemu/common/aarch64/plat_helpers.S
+
+INCLUDES += -Iinclude/services/trp
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 903c809..4e0b50a 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -171,7 +171,8 @@
#define BL32_SRAM_BASE BL_RAM_BASE
#define BL32_SRAM_LIMIT BL31_BASE
#define BL32_DRAM_BASE SEC_DRAM_BASE
-#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
+#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ RME_GPT_DRAM_SIZE)
#define SEC_SRAM_ID 0
#define SEC_DRAM_ID 1
@@ -199,7 +200,7 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_MMAP_REGIONS (11 + MAX_MMAP_REGIONS_SPMC)
+#define MAX_MMAP_REGIONS (13 + MAX_MMAP_REGIONS_SPMC)
#define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC)
#define MAX_IO_DEVICES 4
#define MAX_IO_HANDLES 4
@@ -226,7 +227,7 @@
#define QEMU_FLASH1_SIZE 0x04000000
#define PLAT_QEMU_FIP_BASE 0x00040000
-#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
+#define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - PLAT_QEMU_FIP_BASE)
#define DEVICE0_BASE 0x08000000
#define DEVICE0_SIZE 0x01000000
@@ -338,4 +339,72 @@
#define MAX_MMAP_REGIONS_SPMC 0
#define MAX_XLAT_TABLES_SPMC 0
#endif
+
+#if ENABLE_RME
+
+/*
+ * Reserve some space at the end of secure DRAM for the Granule Protection
+ * Tables
+ */
+#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
+ PLAT_QEMU_L0_GPT_SIZE)
+#define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE)
+
+#define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ PLAT_QEMU_L1_GPT_SIZE)
+#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
+ PLAT_QEMU_L1_GPT_SIZE - 1U)
+#define PLAT_QEMU_L1_GPT_SIZE UL(0x00100000) /* 1MB */
+
+#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
+#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
+ PLAT_QEMU_L0_GPT_SIZE)
+
+#ifndef __ASSEMBLER__
+/* L0 table greater than 4KB must be naturally aligned */
+CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
+ assert_l0_gpt_naturally_aligned);
+#endif
+
+/* Reserved some DRAM space for RMM (24MB) */
+#define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE)
+#define REALM_DRAM_SIZE 0x01800000
+
+#define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE)
+#define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
+
+#define RMM_BASE (REALM_DRAM_BASE)
+#define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE)
+#define RMM_SHARED_BASE (RMM_LIMIT)
+#define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE
+
+#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L0_GPT_BASE, \
+ PLAT_QEMU_L0_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L1_GPT_BASE, \
+ PLAT_QEMU_L1_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+/*
+ * We add the RMM_SHARED size to RMM mapping to map the region as a block.
+ * Else we end up requiring more pagetables in BL2 for ROMLIB build.
+ */
+#define MAP_RMM_DRAM MAP_REGION_FLAT( \
+ RMM_BASE, \
+ (PLAT_QEMU_RMM_SIZE + \
+ RMM_SHARED_SIZE), \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \
+ RMM_SHARED_BASE, \
+ RMM_SHARED_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+#else /* !ENABLE_RME */
+
+#define RME_GPT_DRAM_SIZE 0
+
+#endif /* ENABLE_RME */
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/qemu/qemu/include/qemu_pas_def.h b/plat/qemu/qemu/include/qemu_pas_def.h
new file mode 100644
index 0000000..c108920
--- /dev/null
+++ b/plat/qemu/qemu/include/qemu_pas_def.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef QEMU_PAS_DEF_H
+#define QEMU_PAS_DEF_H
+
+#include <lib/gpt_rme/gpt_rme.h>
+#include "platform_def.h"
+
+/*****************************************************************************
+ * PAS regions used to initialize the Granule Protection Table (GPT)
+ ****************************************************************************/
+
+/*
+ * The PA space is initially mapped in the GPT as follows:
+ *
+ * ===========================================================================
+ * Base Addr | Size |L? GPT|PAS |Content |Comment
+ * ===========================================================================
+ * | 1GB |L0 GPT|ANY |Flash |
+ * 00000000 | | | |IO |
+ * ---------------------------------------------------------------------------
+ * 224MB | 1KB |L0 GPT|ANY |Secure RAM (EL3) |
+ * 0e000000 | | | | (shared) |
+ * ---------------------------------------------------------------------------
+ * | 1MB-1KB |L1 GPT|ROOT |Secure RAM (EL3) |
+ * 0e001000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 225MB | 14MB |L1 GPT|SECURE|Secure RAM |
+ * 0e100000 | | | | (EL2, EL1) |
+ * ---------------------------------------------------------------------------
+ * | 1MB+8KB |L1 GPT|ROOT |L0 and L1 GPTs |
+ * 0eefe000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 240MB | 800MB |L0 GPT|ANY |IO |
+ * 0f000000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 1GB | 1MB |L1 GPT|NS |DRAM |
+ * 40000000 | | | | (device tree) |
+ * ---------------------------------------------------------------------------
+ * 1GB+1MB | 24MB |L1 GPT|REALM |DRAM (RMM) |
+ * 40100000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 1GB+25MB | 3GB |L1 GPT|NS |DRAM (kernel) | Limit set by
+ * 41900000 | | | | | NS_DRAM0_SIZE
+ * ---------------------------------------------------------------------------
+ * 256GB | 512+GB |L0 GPT|ANY |IO | Floating. Higher
+ * 40000000000 | | | | | when RAM>256GB
+ * ----------------------------------------------------------------------------
+ */
+
+/* EL3 SRAM */
+#define QEMU_PAS_ROOT_BASE BL_RAM_BASE
+#define QEMU_PAS_ROOT_SIZE BL_RAM_SIZE
+
+/* Secure DRAM */
+#define QEMU_PAS_SEC_BASE SEC_DRAM_BASE
+#define QEMU_PAS_SEC_SIZE (SEC_DRAM_SIZE - RME_GPT_DRAM_SIZE)
+
+/* GPTs */
+#define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE
+#define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE
+
+/* RMM */
+#define QEMU_PAS_RMM_BASE RMM_BASE
+#define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE
+
+/* Shared area between EL3 and RMM */
+#define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE
+#define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE
+
+#define QEMU_PAS_NS0_BASE NS_DRAM0_BASE
+#define QEMU_PAS_NS0_SIZE PLAT_QEMU_DT_MAX_SIZE
+#define QEMU_PAS_NS1_BASE (REALM_DRAM_BASE + REALM_DRAM_SIZE)
+#define QEMU_PAS_NS1_SIZE (NS_DRAM0_SIZE - \
+ (QEMU_PAS_NS0_SIZE + REALM_DRAM_SIZE))
+
+#define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
+ QEMU_PAS_ROOT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
+ QEMU_PAS_SEC_SIZE, \
+ GPT_GPI_SECURE)
+
+#define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
+ QEMU_PAS_GPT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS0_BASE, \
+ QEMU_PAS_NS0_SIZE, \
+ GPT_GPI_NS)
+
+#define QEMU_PAS_NS1 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS1_BASE, \
+ QEMU_PAS_NS1_SIZE, \
+ GPT_GPI_NS)
+
+#define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
+ QEMU_PAS_RMM_SIZE + \
+ QEMU_PAS_RMM_SHARED_SIZE, \
+ GPT_GPI_REALM)
+
+/* GPT Configuration options */
+#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS
+
+#endif /* QEMU_PAS_DEF_H */
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index e902c12..436e425 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -204,6 +204,10 @@
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
+ ifeq (${ENABLE_RME},1)
+ # Avoid overlap between BL2 and BL32 to ease GPT partition
+ $(error "With RME, BL32 must use secure DRAM")
+ endif
else ifeq (${BL32_RAM_LOCATION}, tdram)
BL32_RAM_LOCATION_ID = SEC_DRAM_ID
else
diff --git a/plat/qemu/qemu/trp/trp-qemu.mk b/plat/qemu/qemu/trp/trp-qemu.mk
new file mode 100644
index 0000000..e0f530e
--- /dev/null
+++ b/plat/qemu/qemu/trp/trp-qemu.mk
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/qemu/common/trp/trp-qemu-common.mk
+
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
index 05ebec4..da40c78 100644
--- a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
+++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
@@ -28,13 +28,102 @@
#define SIP_SVC_VERSION SIP_FUNCTION_ID(1)
#define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100)
#define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
+#define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
+#define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201)
static uint64_t gic_its_addr;
+typedef struct {
+ uint32_t nodeid;
+ uint32_t mpidr;
+} cpu_data;
+
+static struct {
+ uint32_t num_cpus;
+ cpu_data cpu[PLATFORM_CORE_COUNT];
+} dynamic_platform_info;
+
void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base);
uintptr_t sbsa_get_gicd(void);
uintptr_t sbsa_get_gicr(void);
+/*
+ * QEMU provides us with minimal information about hardware platform using
+ * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
+ * a firmware DeviceTree.
+ *
+ * It is information passed from QEMU to describe the information a hardware
+ * platform would have other mechanisms to discover at runtime, that are
+ * affected by the QEMU command line.
+ *
+ * Ultimately this device tree will be replaced by IPC calls to an emulated SCP.
+ * And when we do that, we won't then have to rewrite Normal world firmware to
+ * cope.
+ */
+
+void read_cpuinfo_from_dt(void *dtb)
+{
+ int node;
+ int prev;
+ int cpu = 0;
+ uint32_t nodeid = 0;
+ uintptr_t mpidr;
+
+ /*
+ * QEMU gives us this DeviceTree node:
+ * numa-node-id entries are only when NUMA config is used
+ *
+ * cpus {
+ * #size-cells = <0x00>;
+ * #address-cells = <0x02>;
+ *
+ * cpu@0 {
+ * numa-node-id = <0x00>;
+ * reg = <0x00 0x00>;
+ * };
+ *
+ * cpu@1 {
+ * numa-node-id = <0x03>;
+ * reg = <0x00 0x01>;
+ * };
+ * };
+ */
+ node = fdt_path_offset(dtb, "/cpus");
+ if (node < 0) {
+ ERROR("No information about cpus in DeviceTree.\n");
+ panic();
+ }
+
+ /*
+ * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we
+ * cannot use fdt_first_subnode() here
+ */
+ node = fdt_path_offset(dtb, "/cpus/cpu@0");
+
+ while (node > 0) {
+ if (fdt_getprop(dtb, node, "reg", NULL)) {
+ fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL);
+ }
+
+ if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
+ fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
+ }
+
+ dynamic_platform_info.cpu[cpu].nodeid = nodeid;
+ dynamic_platform_info.cpu[cpu].mpidr = mpidr;
+
+ INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr);
+
+ cpu++;
+
+ prev = node;
+ node = fdt_next_subnode(dtb, prev);
+ }
+
+ dynamic_platform_info.num_cpus = cpu;
+ INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
+}
+
void read_platform_config_from_dt(void *dtb)
{
int node;
@@ -129,6 +218,7 @@
INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor);
read_platform_config_from_dt(dtb);
+ read_cpuinfo_from_dt(dtb);
}
/*
@@ -144,6 +234,7 @@
u_register_t flags)
{
uint32_t ns;
+ uint64_t index;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
@@ -163,6 +254,19 @@
case SIP_SVC_GET_GIC_ITS:
SMC_RET2(handle, NULL, gic_its_addr);
+ case SIP_SVC_GET_CPU_COUNT:
+ SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus);
+
+ case SIP_SVC_GET_CPU_NODE:
+ index = x1;
+ if (index < PLATFORM_CORE_COUNT) {
+ SMC_RET3(handle, NULL,
+ dynamic_platform_info.cpu[index].nodeid,
+ dynamic_platform_info.cpu[index].mpidr);
+ } else {
+ SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
+ }
+
default:
ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid,
smc_fid - SIP_FUNCTION);
diff --git a/plat/xilinx/common/include/plat_clkfunc.h b/plat/xilinx/common/include/plat_clkfunc.h
new file mode 100644
index 0000000..a182f91
--- /dev/null
+++ b/plat/xilinx/common/include/plat_clkfunc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_CLKFUNC_H
+#define PLAT_CLKFUNC_H
+
+void set_cnt_freq(void);
+
+#endif /* PLAT_CLKFUNC_H */
diff --git a/plat/xilinx/common/plat_clkfunc.c b/plat/xilinx/common/plat_clkfunc.c
new file mode 100644
index 0000000..8a8ea7e
--- /dev/null
+++ b/plat/xilinx/common/plat_clkfunc.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+#include <plat_private.h>
+
+uint32_t plat_get_syscnt_freq2(void)
+{
+ uint32_t counter_freq = 0;
+ uint32_t ret = 0;
+
+ counter_freq = mmio_read_32(IOU_SCNTRS_BASE +
+ IOU_SCNTRS_BASE_FREQ_OFFSET);
+ if (counter_freq != 0U) {
+ ret = counter_freq;
+ } else {
+ INFO("Indicates counter frequency %dHz setting to %dHz\n",
+ counter_freq, cpu_clock);
+ ret = cpu_clock;
+ }
+
+ return ret;
+}
+
+void set_cnt_freq(void)
+{
+ uint64_t counter_freq;
+
+ /* Configure counter frequency */
+ counter_freq = read_cntfrq_el0();
+ if (counter_freq == 0U) {
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+ }
+}
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index aba190d..772477f 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -18,6 +18,7 @@
#include <versal_def.h>
uint32_t platform_id, platform_version;
+uint32_t cpu_clock = VERSAL_CPU_CLOCK;
/*
* Table of regions to map using the MMU.
@@ -53,11 +54,6 @@
generic_delay_timer_init();
}
-uint32_t plat_get_syscnt_freq2(void)
-{
- return VERSAL_CPU_CLOCK;
-}
-
void board_detection(void)
{
uint32_t plat_info[2];
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index cd105c6..d19a263 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -17,6 +17,7 @@
#include <plat/common/platform.h>
#include <plat_arm.h>
#include <plat_console.h>
+#include <plat_clkfunc.h>
#include <plat_fdt.h>
#include <plat_private.h>
@@ -72,6 +73,8 @@
enum pm_ret_status ret_status;
uint64_t addr[HANDOFF_PARAMS_MAX_SIZE];
+ set_cnt_freq();
+
setup_console();
/* Initialize the platform config for future decision making */
diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h
index a4210cd..932c6de 100644
--- a/plat/xilinx/versal/include/plat_private.h
+++ b/plat/xilinx/versal/include/plat_private.h
@@ -22,7 +22,7 @@
const mmap_region_t *plat_get_mmap(void);
-extern uint32_t platform_id, platform_version;
+extern uint32_t cpu_clock, platform_id, platform_version;
void board_detection(void);
void plat_versal_gic_driver_init(void);
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 92c0ba6..f21d409 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -111,6 +111,10 @@
#define CRF_RST_APU_ACPU_RESET (1 << 0)
#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
+/* IOU SCNTRS */
+#define IOU_SCNTRS_BASE U(0xFF140000)
+#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
+
/* APU registers and bitfields */
#define FPD_APU_BASE 0xFD5C0000U
#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 612e956..35d6bc7 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -96,6 +96,7 @@
plat/xilinx/common/ipi.c \
plat/xilinx/common/plat_fdt.c \
plat/xilinx/common/plat_console.c \
+ plat/xilinx/common/plat_clkfunc.c \
plat/xilinx/common/plat_startup.c \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/pm_service/pm_ipi.c \
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index 69c5c87..55c4198 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -114,11 +114,21 @@
void versal_net_config_setup(void)
{
+ generic_delay_timer_init();
+
+#if (TFA_NO_PM == 0)
+ /* Configure IPI data for versal_net */
+ versal_net_ipi_config_table_init();
+#endif
+}
+
+void syscnt_freq_config_setup(void)
+{
uint32_t val;
uintptr_t crl_base, iou_scntrs_base, psx_base;
crl_base = VERSAL_NET_CRL;
- iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
+ iou_scntrs_base = IOU_SCNTRS_BASE;
psx_base = PSX_CRF;
/* Reset for system timestamp generator in FPX */
@@ -133,20 +143,9 @@
mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
/* Program freq register in System counter and enable system counter. */
- mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET,
cpu_clock);
- mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
- VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
-
- generic_delay_timer_init();
-
-#if (TFA_NO_PM == 0)
- /* Configure IPI data for versal_net */
- versal_net_ipi_config_table_init();
-#endif
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
+ IOU_SCNTRS_CONTROL_EN);
}
-uint32_t plat_get_syscnt_freq2(void)
-{
- return cpu_clock;
-}
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 56ef27b..283fee3 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -17,6 +17,7 @@
#include <plat/common/platform.h>
#include <plat_arm.h>
#include <plat_console.h>
+#include <plat_clkfunc.h>
#include <plat_fdt.h>
#include <plat_private.h>
@@ -93,6 +94,10 @@
panic();
}
+ syscnt_freq_config_setup();
+
+ set_cnt_freq();
+
setup_console();
NOTICE("TF-A running on %s %d.%d\n", board_name_decode(),
diff --git a/plat/xilinx/versal_net/include/plat_private.h b/plat/xilinx/versal_net/include/plat_private.h
index 9cd8636..0b82ca7 100644
--- a/plat/xilinx/versal_net/include/plat_private.h
+++ b/plat/xilinx/versal_net/include/plat_private.h
@@ -18,6 +18,7 @@
} versal_intr_info_type_el3_t;
void versal_net_config_setup(void);
+void syscnt_freq_config_setup(void);
uint32_t get_uart_clk(void);
const mmap_region_t *plat_get_mmap(void);
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index dd20faa..e7d234b 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -111,11 +111,11 @@
#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
/* IOU SCNTRS */
-#define VERSAL_NET_IOU_SCNTRS U(0xEC920000)
-#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
-#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
+#define IOU_SCNTRS_BASE U(0xEC920000)
+#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
+#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
-#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1)
+#define IOU_SCNTRS_CONTROL_EN U(1)
#define APU_CLUSTER0 U(0xECC00000)
#define APU_RVBAR_L_0 U(0x40)
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index 65ebaaa..ad1ee2b 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -114,6 +114,7 @@
BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
plat/xilinx/common/plat_startup.c \
plat/xilinx/common/plat_console.c \
+ plat/xilinx/common/plat_clkfunc.c \
plat/xilinx/common/ipi.c \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/versal.c \
diff --git a/services/std_svc/rmmd/rmmd.mk b/services/std_svc/rmmd/rmmd.mk
index bcf54e1..eae5031 100644
--- a/services/std_svc/rmmd/rmmd.mk
+++ b/services/std_svc/rmmd/rmmd.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,7 +8,10 @@
$(error "Error: RMMD is only supported on aarch64.")
endif
-include services/std_svc/rmmd/trp/trp.mk
+# Include TRP makefile only if RMM is not defined.
+ifeq ($(RMM),)
+ include services/std_svc/rmmd/trp/trp.mk
+endif
RMMD_SOURCES += $(addprefix services/std_svc/rmmd/, \
${ARCH}/rmmd_helpers.S \
diff --git a/tools/memory/memory/mapparser.py b/tools/memory/memory/mapparser.py
index b1a4b4c..ce4cc31 100644
--- a/tools/memory/memory/mapparser.py
+++ b/tools/memory/memory/mapparser.py
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -57,7 +57,7 @@
if "start" and "length" and "end" in memory_layout[region]:
memory_layout[region]["limit"] = (
- memory_layout[region]["end"]
+ memory_layout[region]["start"]
+ memory_layout[region]["length"]
)
memory_layout[region]["free"] = (