diff --git a/fdts/tc-common.dtsi b/fdts/tc-common.dtsi
new file mode 100644
index 0000000..c331193
--- /dev/null
+++ b/fdts/tc-common.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define PASTER(x, y)		x ## y
+#define EVALUATOR(x, y)		PASTER(x, y)
+#define ADDRESSIFY(addr)	EVALUATOR(0x, addr)
diff --git a/fdts/tc.dts b/fdts/tc.dts
index 63f6c3d..032c452 100644
--- a/fdts/tc.dts
+++ b/fdts/tc.dts
@@ -9,6 +9,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "platform_def.h"
+
+#include "tc-common.dtsi"
 #include "tc_vers.dtsi"
 #if TARGET_FLAVOUR_FVP
 #include "tc_fvp.dtsi"
@@ -386,9 +388,9 @@
 		};
 	};
 
-	mbox_db_rx: mhu@MHU_RX_ADDR() {
+	mbox_db_rx: mhu@MHU_RX_ADDR {
 		compatible = "arm,mhuv2-rx","arm,primecell";
-		reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
+		reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>;
 		clocks = <&soc_refclk>;
 		clock-names = "apb_pclk";
 		#mbox-cells = <2>;
@@ -398,9 +400,9 @@
 		arm,mhuv2-protocols = <0 1>;
 	};
 
-	mbox_db_tx: mhu@MHU_TX_ADDR() {
+	mbox_db_tx: mhu@MHU_TX_ADDR {
 		compatible = "arm,mhuv2-tx","arm,primecell";
-		reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
+		reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>;
 		clocks = <&soc_refclk>;
 		clock-names = "apb_pclk";
 		#mbox-cells = <2>;
@@ -606,11 +608,11 @@
 	};
 #endif /* TC_IOMMU_EN */
 
-	dp0: display@DPU_ADDR() {
+	dp0: display@DPU_ADDR {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "arm,mali-d71";
-		reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
+		reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>;
 		interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "DPU";
 		DPU_CLK_ATTR1;
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
index 43fafd5..aa3c89f 100644
--- a/fdts/tc_vers.dtsi
+++ b/fdts/tc_vers.dtsi
@@ -28,8 +28,8 @@
 #endif /* TARGET_FLAVOUR_FPGA */
 
 #define INT_MBOX_RX		317
-#define MHU_TX_ADDR(pref)	pref##45000000 /* hex */
-#define MHU_RX_ADDR(pref)	pref##45010000 /* hex */
+#define MHU_TX_ADDR		45000000 /* hex */
+#define MHU_RX_ADDR		45010000 /* hex */
 #define MPAM_ADDR		0x1 0x00010000 /* 0x1_0001_0000 */
 #define UARTCLK_FREQ		5000000
 #elif TARGET_PLATFORM == 3
@@ -38,8 +38,8 @@
 #define MID_CAPACITY		686
 
 #define INT_MBOX_RX		300
-#define MHU_TX_ADDR(pref)	pref##46040000 /* hex */
-#define MHU_RX_ADDR(pref)	pref##46140000 /* hex */
+#define MHU_TX_ADDR		46040000 /* hex */
+#define MHU_RX_ADDR		46140000 /* hex */
 #define MPAM_ADDR		0x0 0x5f010000 /* 0x5f01_0000 */
 #define UARTCLK_FREQ		3750000
 #endif /* TARGET_PLATFORM == 3 */
@@ -63,10 +63,10 @@
 #define ETH_COMPATIBLE		"smsc,lan91c111"
 #define MMC_REMOVABLE		cd-gpios = <&sysreg 0 0>
 #if TARGET_PLATFORM <= 2
-#define DPU_ADDR(pref)		pref##2cc00000
+#define DPU_ADDR		2cc00000
 #define DPU_IRQ			69
 #else /* TARGET_PLATFORM >= 3 */
-#define DPU_ADDR(pref)		pref##4000000000
+#define DPU_ADDR		4000000000
 #define DPU_IRQ			579
 #endif /* TARGET_PLATFORM >= 3 */
 
@@ -90,7 +90,7 @@
 	vsync-len = <10>
 #define ETH_COMPATIBLE		"smsc,lan9115"
 #define MMC_REMOVABLE		non-removable
-#define DPU_ADDR(pref)		pref##2cc00000
+#define DPU_ADDR		2cc00000
 #define DPU_IRQ			69
 #endif /* TARGET_FLAVOUR_FPGA */