commit ade9ce03b867e0df5886b81888ad05a8905c0728
author Yann Gautier <yann.gautier@st.com> Tue May 05 17:58:40 2020 +0200
committer Yann Gautier <yann.gautier@st.com> Tue Oct 13 11:27:40 2020 +0200
tree cc9b85cae3b79cff94576b9c65258bfd8336eb90
parent f964f5c363bc0f690520153741f0f22226e871cc

stm32mp1: get peripheral base address from a define

Retrieve peripheral base address from a define instead of
parsing the device tree. The goal is to improve execution time.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b

drivers/st/clk/stm32mp1_clk.c

diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index f8bc5a2..564bd87 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -1664,28 +1664,26 @@
 
 static void stm32mp1_stgen_config(void)
 {
-	uintptr_t stgen;
 	uint32_t cntfid0;
 	unsigned long rate;
 	unsigned long long counter;
 
-	stgen = fdt_get_stgen_base();
-	cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
+	cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
 	rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
 
 	if (cntfid0 == rate) {
 		return;
 	}
 
-	mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
-	counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
-	counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
+	mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+	counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
+	counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
 	counter = (counter * rate / cntfid0);
 
-	mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
-	mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
-	mmio_write_32(stgen + CNTFID_OFF, rate);
-	mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+	mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
+	mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
+	mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
+	mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
 
 	write_cntfrq((u_register_t)rate);
 
@@ -1695,20 +1693,17 @@
 
 void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
 {
-	uintptr_t stgen;
 	unsigned long long cnt;
 
-	stgen = fdt_get_stgen_base();
+	cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
+		mmio_read_32(STGEN_BASE + CNTCVL_OFF);
 
-	cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
-		mmio_read_32(stgen + CNTCVL_OFF);
+	cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
 
-	cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
-
-	mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
-	mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
-	mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
-	mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
+	mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
+	mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
+	mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
+	mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
 }
 
 static void stm32mp1_pkcs_config(uint32_t pkcs)