fix(cpus): workaround for Cortex-A720-AE erratum 3699562
Cortex-A720-AE erratum 3699562 that applies to r0p0 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3090091/latest/
Change-Id: Ib830470747822cac916750c01684a65cb5efc15b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S
index 42d49c3..57a5030 100644
--- a/lib/cpus/aarch64/cortex_a720_ae.S
+++ b/lib/cpus/aarch64/cortex_a720_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,12 @@
#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+.global check_erratum_cortex_a720_ae_3699562
+
+add_erratum_entry cortex_a720_ae, ERRATUM(3699562), ERRATA_A720_AE_3699562, NO_APPLY_AT_RESET
+
+check_erratum_ls cortex_a720_ae, ERRATUM(3699562), CPU_REV(0, 0)
+
cpu_reset_func_start cortex_a720_ae
/* Disable speculative loads */
msr SSBS, xzr
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 68a50fc..75d5ad2 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1015,6 +1015,11 @@
# the Cortex-A720 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A720_3699561
+# Flag to apply erratum 3699562 workaround during context save/restore of
+# ICH_VMCR_EL2 reg. This erratum applies to revision r0p0 the Cortex-A720-AE
+# cpu and is still open.
+CPU_FLAG_LIST += ERRATA_A720_AE_3699562
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index e5d14d5..a6be68a 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -13,6 +13,7 @@
#include <cortex_a710.h>
#include <cortex_a715.h>
#include <cortex_a720.h>
+#include <cortex_a720_ae.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -68,6 +69,13 @@
break;
#endif /* ERRATA_A720_3699561 */
+#if ERRATA_A720_AE_3699562
+ case EXTRACT_PARTNUM(CORTEX_A720_AE_MIDR):
+ if (check_erratum_cortex_a720_ae_3699562(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A720_AE_3699562 */
+
default:
break;
}