diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c
index 3a9859c..06fe88e 100644
--- a/drivers/marvell/mci.c
+++ b/drivers/marvell/mci.c
@@ -245,7 +245,7 @@
 				MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
 #define MCI_PHY_CTRL_PIDI_MODE_OFFSET			31
 #define MCI_PHY_CTRL_PIDI_MODE				\
-				(1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
+				(1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
 
 /* Number of times to wait for the MCI link ready after MCI configurations
  * Normally takes 34-35 successive reads
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index d7d7373..b4b4e0c 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -56,11 +56,11 @@
 				(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET	16
 #define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK	\
-				(0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
+				(0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
 
 #define MVEBU_SAMPLE_AT_RESET_REG	(0x440600)
 #define SAR_PCIE1_CLK_CFG_OFFSET	31
-#define SAR_PCIE1_CLK_CFG_MASK		(0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
+#define SAR_PCIE1_CLK_CFG_MASK		(0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
 #define SAR_PCIE0_CLK_CFG_OFFSET	30
 #define SAR_PCIE0_CLK_CFG_MASK		(0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
 #define SAR_I2C_INIT_EN_OFFSET		24