| commit | 553b70c3ef0b21795352f8fa275a7c15c01c826a | [log] [tgz] |
|---|---|---|
| author | Manish V Badarkhe <manish.badarkhe@arm.com> | Mon Aug 19 11:56:49 2024 +0200 |
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | Mon Aug 19 11:56:49 2024 +0200 |
| tree | dcb5c4a32028ecf0c2aada17b27d6648134dedb1 | |
| parent | 2d4f264ba5ffd8a08c99f54c02a103ca7c8ffa78 [diff] | |
| parent | 74dc801d4b284e0b3829ab8ec741e0f2c311a7c2 [diff] |
Merge changes from topic "ar/asymmetricSupport" into integration * changes: feat(tc): enable trbe errata flags for Cortex-A520 and X4 feat(cm): asymmetric feature support for trbe refactor(errata-abi): move EXTRACT_PARTNUM to arch.h feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228) feat(tc): make SPE feature asymmetric feat(cm): handle asymmetry for SPE feature feat(cm): support for asymmetric feature among cores feat(cpufeat): add new feature state for asymmetric features