tree f5b43d070da9c3fc92fce92929d40059859ef782
parent 61a29682c66d0437806f81fb8ab0e3ff321dfe04
author Rohit Mathew <Rohit.Mathew@arm.com> 1702644658 +0000
committer Rohit Mathew <Rohit.Mathew@arm.com> 1704395198 +0000

feat(cpu): add support for Poseidon V CPU

Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhancement ensures compatibility with RD-Fremont and similar
platforms utilizing Poseidon V CPUs.

CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189