diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h
index ddb235f..1edef84 100644
--- a/include/lib/cpus/aarch64/aem_generic.h
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __AEM_GENERIC_H__
-#define __AEM_GENERIC_H__
+#ifndef AEM_GENERIC_H
+#define AEM_GENERIC_H
 
 /* BASE AEM midr for revision 0 */
 #define BASE_AEM_MIDR 0x410FD0F0
@@ -13,5 +13,4 @@
 /* Foundation AEM midr for revision 0 */
 #define FOUNDATION_AEM_MIDR  0x410FD000
 
-
-#endif /* __AEM_GENERIC_H__ */
+#endif /* AEM_GENERIC_H */
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h
index ad0fedc..2363198 100644
--- a/include/lib/cpus/aarch64/cortex_a35.h
+++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A35_H__
-#define __CORTEX_A35_H__
+#ifndef CORTEX_A35_H
+#define CORTEX_A35_H
 
 /* Cortex-A35 Main ID register for revision 0 */
 #define CORTEX_A35_MIDR				0x410FD040
@@ -17,4 +17,4 @@
 #define CORTEX_A35_CPUECTLR_EL1			S3_1_C15_C2_1
 #define CORTEX_A35_CPUECTLR_SMPEN_BIT		(1 << 6)
 
-#endif /* __CORTEX_A35_H__ */
+#endif /* CORTEX_A35_H */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 9aa118b..4b7d238 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A53_H__
-#define __CORTEX_A53_H__
+#ifndef CORTEX_A53_H
+#define CORTEX_A53_H
 
 /* Cortex-A53 midr for revision 0 */
 #define CORTEX_A53_MIDR			U(0x410FD030)
@@ -71,4 +71,4 @@
  ******************************************************************************/
 #define CORTEX_A53_L2MERRSR_EL1				S3_1_C15_C2_3
 
-#endif /* __CORTEX_A53_H__ */
+#endif /* CORTEX_A53_H */
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index 293f2b2..763b7cb 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A55_H__
-#define __CORTEX_A55_H__
+#ifndef CORTEX_A55_H
+#define CORTEX_A55_H
 
 /* Cortex-A55 MIDR for revision 0 */
 #define CORTEX_A55_MIDR		0x410fd050
@@ -19,4 +19,4 @@
 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
 #define CORTEX_A55_CORE_PWRDN_EN_MASK	0x1
 
-#endif /* __CORTEX_A55_H__ */
+#endif /* CORTEX_A55_H */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 97d074e..71d07db 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A57_H__
-#define __CORTEX_A57_H__
+#ifndef CORTEX_A57_H
+#define CORTEX_A57_H
 #include <utils_def.h>
 
 /* Cortex-A57 midr for revision 0 */
@@ -81,4 +81,4 @@
  ******************************************************************************/
 #define CORTEX_A57_L2MERRSR_EL1			S3_1_C15_C2_3
 
-#endif /* __CORTEX_A57_H__ */
+#endif /* CORTEX_A57_H */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 5b9e06d..4eafc11 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A72_H__
-#define __CORTEX_A72_H__
+#ifndef CORTEX_A72_H
+#define CORTEX_A72_H
 #include <utils_def.h>
 
 /* Cortex-A72 midr for revision 0 */
@@ -61,4 +61,4 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
 
-#endif /* __CORTEX_A72_H__ */
+#endif /* CORTEX_A72_H */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h
index 4db0cae..77ea205 100644
--- a/include/lib/cpus/aarch64/cortex_a73.h
+++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A73_H__
-#define __CORTEX_A73_H__
+#ifndef CORTEX_A73_H
+#define CORTEX_A73_H
 
 /* Cortex-A73 midr for revision 0 */
 #define CORTEX_A73_MIDR	0x410FD090
@@ -29,4 +29,4 @@
 
 #define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE	(1 << 3)
 
-#endif /* __CORTEX_A73_H__ */
+#endif /* CORTEX_A73_H */
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 1cb7747..4dea64b 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_A76_H__
-#define __CORTEX_A76_H__
+#ifndef CORTEX_A76_H
+#define CORTEX_A76_H
 
 /* Cortex-A76 MIDR for revision 0 */
 #define CORTEX_A76_MIDR		0x410fd0b0
@@ -26,4 +26,4 @@
 /* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
 #define CORTEX_A76_CORE_PWRDN_EN_MASK	0x1
 
-#endif /* __CORTEX_A76_H__ */
+#endif /* CORTEX_A76_H */
diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h
index 3c36567..694fb15 100644
--- a/include/lib/cpus/aarch64/cortex_deimos.h
+++ b/include/lib/cpus/aarch64/cortex_deimos.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_DEIMOS_H__
-#define __CORTEX_DEIMOS_H__
+#ifndef CORTEX_DEIMOS_H
+#define CORTEX_DEIMOS_H
 
 #define CORTEX_DEIMOS_MIDR					U(0x410FD0D0)
 
@@ -20,4 +20,4 @@
 #define CORTEX_DEIMOS_CPUPWRCTLR_EL1				S3_0_C15_C2_7
 #define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		(U(1) << 0)
 
-#endif /* __CORTEX_DEIMOS_H__ */
+#endif /* CORTEX_DEIMOS_H */
diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h
index 1098a12..571ea9d 100644
--- a/include/lib/cpus/aarch64/cortex_helios.h
+++ b/include/lib/cpus/aarch64/cortex_helios.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __CORTEX_HELIOS_H__
-#define __CORTEX_HELIOS_H__
+#ifndef CORTEX_HELIOS_H
+#define CORTEX_HELIOS_H
 
 #define CORTEX_HELIOS_MIDR		U(0x410FD060)
 
@@ -26,4 +26,4 @@
 #define CORTEX_HELIOS_CPUPWRCTLR_EL1				S3_0_C15_C2_7
 #define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT		(U(1) << 0)
 
-#endif /* __CORTEX_HELIOS_H__ */
+#endif /* CORTEX_HELIOS_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 14616ac..2875700 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef __CPU_MACROS_S__
-#define __CPU_MACROS_S__
+#ifndef CPU_MACROS_S
+#define CPU_MACROS_S
 
 #include <arch.h>
 #include <errata_report.h>
@@ -255,8 +255,6 @@
 	.endm
 #endif
 
-#endif /* __CPU_MACROS_S__ */
-
 	/*
 	 * This macro is used on some CPUs to detect if they are vulnerable
 	 * to CVE-2017-5715.
@@ -285,3 +283,5 @@
 	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
 	b.eq	\_label
 	.endm
+
+#endif /* CPU_MACROS_S */
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 712a4a4..81c076a 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __DENVER_H__
-#define __DENVER_H__
+#ifndef DENVER_H
+#define DENVER_H
 
 /* MIDR values for Denver */
 #define DENVER_MIDR_PN0			U(0x4E0F0000)
@@ -39,6 +39,6 @@
 /* Disable Dynamic Code Optimisation */
 void denver_disable_dco(void);
 
-#endif
+#endif /* __ASSEMBLY__ */
 
-#endif /* __DENVER_H__ */
+#endif /* DENVER_H */