diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 95fe50e..53946ab 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -25,6 +25,10 @@
 BL1_SOURCES		+=	bl1/bl1_fwu.c
 endif
 
+ifeq (${ENABLE_PMF},1)
+BL1_SOURCES		+=	lib/pmf/pmf_main.c
+endif
+
 ifneq ($(findstring gcc,$(notdir $(LD))),)
         BL1_LDFLAGS	+=	-Wl,--sort-section=alignment
 else ifneq ($(findstring ld,$(notdir $(LD))),)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 3f64e27..6fe5511 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,9 @@
 #include <drivers/auth/auth_mod.h>
 #include <drivers/auth/crypto_mod.h>
 #include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
 #include <lib/cpus/errata.h>
+#include <lib/pmf/pmf.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 #include <smccc_helpers.h>
@@ -31,6 +33,11 @@
 uint64_t bl1_apiakey[2];
 #endif
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+		BL_TOTAL_IDS, PMF_DUMP_ENABLE)
+#endif
+
 /*******************************************************************************
  * Helper utility to calculate the BL2 memory layout taking into consideration
  * the BL1 RW data assuming that it is at the top of the memory layout.
@@ -81,6 +88,10 @@
 {
 	unsigned int image_id;
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT);
+#endif
+
 	/* Announce our arrival */
 	NOTICE(FIRMWARE_WELCOME_STR);
 	NOTICE("BL1: %s\n", version_string);
@@ -156,6 +167,10 @@
 
 	bl1_prepare_next_image(image_id);
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT);
+#endif
+
 	console_flush();
 }
 
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 1663c52..b70a3fb 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -49,3 +49,7 @@
 
 BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2_el3.ld.S
 endif
+
+ifeq (${ENABLE_PMF},1)
+BL2_SOURCES		+=	lib/pmf/pmf_main.c
+endif
\ No newline at end of file
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index ce83692..923a554 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -16,7 +16,9 @@
 #include <drivers/auth/crypto_mod.h>
 #include <drivers/console.h>
 #include <drivers/fwu/fwu.h>
+#include <lib/bootmarker_capture.h>
 #include <lib/extensions/pauth.h>
+#include <lib/pmf/pmf.h>
 #include <plat/common/platform.h>
 
 #include "bl2_private.h"
@@ -27,6 +29,11 @@
 #define NEXT_IMAGE	"BL32"
 #endif
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+		BL_TOTAL_IDS, PMF_DUMP_ENABLE);
+#endif
+
 #if RESET_TO_BL2
 /*******************************************************************************
  * Setup function for BL2 when RESET_TO_BL2=1
@@ -81,6 +88,10 @@
 {
 	entry_point_info_t *next_bl_ep_info;
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT);
+#endif
+
 	NOTICE("BL2: %s\n", version_string);
 	NOTICE("BL2: %s\n", build_message);
 
@@ -118,8 +129,6 @@
 	disable_mmu_icache_secure();
 #endif /* !__aarch64__ */
 
-	console_flush();
-
 #if ENABLE_PAUTH
 	/*
 	 * Disable pointer authentication before running next boot image
@@ -127,6 +136,12 @@
 	pauth_disable_el1();
 #endif /* ENABLE_PAUTH */
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
+
+	console_flush();
+
 	/*
 	 * Run next BL image via an SMC to BL1. Information on how to pass
 	 * control to the BL32 (if present) and BL33 software images will
@@ -137,6 +152,9 @@
 
 	NOTICE("BL2: Booting " NEXT_IMAGE "\n");
 	print_entry_point_info(next_bl_ep_info);
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
 	console_flush();
 
 #if ENABLE_PAUTH
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index bf805f5..cae55f3 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,6 +17,7 @@
 #include <common/feat_detect.h>
 #include <common/runtime_svc.h>
 #include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/pmf/pmf.h>
 #include <lib/runtime_instr.h>
@@ -24,8 +25,13 @@
 #include <services/std_svc.h>
 
 #if ENABLE_RUNTIME_INSTRUMENTATION
-PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
-	RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
+	PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
+		RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
+#endif
+
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+		BL_TOTAL_IDS, PMF_DUMP_ENABLE)
 #endif
 
 /*******************************************************************************
@@ -123,6 +129,10 @@
 	detect_arch_features();
 #endif /* FEATURE_DETECTION */
 
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_ENTRY, PMF_CACHE_MAINT);
+#endif
+
 #ifdef SUPPORT_UNKNOWN_MPID
 	if (unsupported_mpid_flag == 0) {
 		NOTICE("Unsupported MPID detected!\n");
@@ -201,6 +211,11 @@
 	 * from BL31
 	 */
 	bl31_plat_runtime_setup();
+
+#if ENABLE_RUNTIME_INSTRUMENTATION
+	PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT);
+	console_flush();
+#endif
 }
 
 /*******************************************************************************
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 5b52bd5..447d108 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -635,6 +635,13 @@
 :|F|: docs/plat/imx8m.rst
 :|F|: plat/imx/imx8m/
 
+NXP i.MX9 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jacky Bai <ping.bai@nxp.com>
+:|G|: `JackyBai`_
+:|F|: docs/plat/imx9.rst
+:|F|: plat/imx/imx93/
+
 NXP QorIQ Layerscape common code for platform ports
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 :|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7bf7760..d1bf0d3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -718,6 +718,10 @@
   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
   CPU, it is still open.
 
+- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
+  Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+  r1p1. It is fixed in r1p2.
+
 For Cortex-A510, the following errata build flags are defined :
 
 -  ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index f4c3c28..332ed58 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -77,7 +77,7 @@
 The following libraries are required for Trusted Board Boot and Measured Boot
 support:
 
-- mbed TLS == 3.4.0 (tag: ``mbedtls-3.4.0``)
+- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``)
 
 These tools are optional:
 
diff --git a/docs/perf/psci-performance-instr.rst b/docs/perf/psci-performance-instr.rst
index 16f386f..41094b2 100644
--- a/docs/perf/psci-performance-instr.rst
+++ b/docs/perf/psci-performance-instr.rst
@@ -13,16 +13,17 @@
 Performance Measurement Framework
 ---------------------------------
 
-The Performance Measurement Framework `PMF`_ is a framework that provides
-mechanisms for collecting and retrieving timestamps at runtime from the
-Performance Measurement Unit (`PMU`_). The PMU is a generalized abstraction for
-accessing CPU hardware registers used to measure hardware events. This means,
-for instance, that the PMU might be used to place instrumentation points at
-logical locations in code for tracing purposes.
+The Performance Measurement Framework :ref:`PMF <firmware_design_pmf>`
+is a framework that provides mechanisms for collecting and retrieving timestamps
+at runtime from the Performance Measurement Unit
+(:ref:`PMU <Performance Monitoring Unit>`).
+The PMU is a generalized abstraction for accessing CPU hardware registers used to
+measure hardware events. This means, for instance, that the PMU might be used to
+place instrumentation points at logical locations in code for tracing purposes.
 
 TF-A utilises the PMF as a backend for the two instrumentation services it
 provides--PSCI Statistics and Runtime Instrumentation. The PMF is used by
-these services to facilitate collection and retrieval of timestamps.  For
+these services to facilitate collection and retrieval of timestamps. For
 instance, the PSCI Statistics service registers the PMF service
 ``psci_svc`` to track its residency statistics.
 
@@ -112,6 +113,4 @@
 
 *Copyright (c) 2023, Arm Limited. All rights reserved.*
 
-.. _PMF: ../design/firmware-design.html#performance-measurement-framework
-.. _PMU: performance-monitoring-unit.html
 .. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 7a484b8..d458d86 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -34,8 +34,9 @@
 - TF-A [`v2.9-rc0`_]
 - TFTF [`v2.9-rc0`_]
 
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>`
+page for more details.
 
 Procedure
 ---------
@@ -418,4 +419,3 @@
 .. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
 .. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
 .. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index 70a1436..ae1b89b 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -10,8 +10,8 @@
 - TFTF [`v2.9-rc0`_]
 - SCP/MCP `Prebuilt Images`_
 
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>` page for more details.
 
 Procedure
 ---------
@@ -200,4 +200,3 @@
 .. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
 .. _Prebuilt Images:  https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
 .. _N1SDP: https://developer.arm.com/documentation/101489/latest
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
\ No newline at end of file
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
index c50ed8e..57a5e1b 100644
--- a/docs/threat_model/threat_model.rst
+++ b/docs/threat_model/threat_model.rst
@@ -85,6 +85,8 @@
   +-----------------+--------------------------------------------------------+
 
 
+.. _threat_analysis:
+
 ***************
 Threat Analysis
 ***************
diff --git a/docs/threat_model/threat_model_el3_spm.rst b/docs/threat_model/threat_model_el3_spm.rst
index c3af7a2..8adf3df 100644
--- a/docs/threat_model/threat_model_el3_spm.rst
+++ b/docs/threat_model/threat_model_el3_spm.rst
@@ -4,7 +4,7 @@
 ************
 Introduction
 ************
-This document provides a threat model for the TF-A `EL3 Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`EL3 Secure Partition Manager`
 (EL3 SPM) implementation. The EL3 SPM implementation is based on the
 `Arm Firmware Framework for Arm A-profile`_ specification.
 
@@ -13,7 +13,8 @@
 ********************
 In this threat model, the target of evaluation is the ``Secure Partition Manager Core``
 component (SPMC) within the EL3 firmware.
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
 
 The scope for this threat model is:
 
@@ -70,8 +71,8 @@
 Threat Analysis
 ***************
 
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
-The following sections define:
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`. The following sections define:
 
 - Trust boundaries
 - Assets
@@ -115,7 +116,8 @@
 Threat types
 ============
 
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
 are re-used:
 
 - Spoofing
@@ -642,9 +644,7 @@
 
 ---------------
 
-*Copyright (c) 2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2023, Arm Limited. All rights reserved.*
 
 .. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _EL3 Secure Partition Manager: ../components/el3-spmc.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
 .. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst
index 9458a9f..24a115b 100644
--- a/docs/threat_model/threat_model_spm.rst
+++ b/docs/threat_model/threat_model_spm.rst
@@ -4,7 +4,7 @@
 ************************
 Introduction
 ************************
-This document provides a threat model for the TF-A `Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`Secure Partition Manager`
 (SPM) implementation or more generally the S-EL2 reference firmware running on
 systems implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) architecture
 extension. The SPM implementation is based on the `Arm Firmware Framework for
@@ -28,7 +28,8 @@
 ************************
 In this threat model, the target of evaluation is the S-EL2 firmware or the
 ``Secure Partition Manager Core`` component (SPMC).
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
 
 The scope for this threat model is:
 
@@ -92,7 +93,8 @@
 Threat Analysis
 *********************
 
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`.
 The following sections define:
 
 - Trust boundaries
@@ -141,7 +143,8 @@
 Threat types
 ============================
 
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
 are re-used:
 
 - Spoofing
@@ -1333,7 +1336,5 @@
 *Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
 
 .. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _Secure Partition Manager: ../components/secure-partition-manager.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
 .. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
 
diff --git a/include/lib/bootmarker_capture.h b/include/lib/bootmarker_capture.h
new file mode 100644
index 0000000..31fe048
--- /dev/null
+++ b/include/lib/bootmarker_capture.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOTMARKER_CAPTURE_H
+#define BOOTMARKER_CAPTURE_H
+
+#define BL1_ENTRY	U(0)
+#define BL1_EXIT	U(1)
+#define BL2_ENTRY	U(2)
+#define BL2_EXIT	U(3)
+#define BL31_ENTRY	U(4)
+#define BL31_EXIT	U(5)
+#define BL_TOTAL_IDS	U(6)
+
+#ifdef __ASSEMBLER__
+PMF_DECLARE_CAPTURE_TIMESTAMP(bl_svc)
+#endif  /*__ASSEMBLER__*/
+
+#endif  /*BOOTMARKER_CAPTURE_H*/
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index ceafe66..e648734 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,4 +31,11 @@
 #define CORTEX_X3_CPUACTLR2_EL1			S3_0_C15_C1_1
 #define CORTEX_X3_CPUACTLR2_EL1_BIT_36		(ULL(1) << 36)
 
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR5_EL1			S3_0_C15_C8_0
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_55		(ULL(1) << 55)
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_56		(ULL(1) << 56)
+
 #endif /* CORTEX_X3_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 9426ac7..0ab0e82 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -593,15 +593,15 @@
  * As the BL31 image size appears to be increased when built with the ENABLE_PIE
  * option, set BL2 base address to have enough space for BL31 in Trusted SRAM.
  */
-#define BL2_BASE			(ARM_TRUSTED_SRAM_BASE + \
-					(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
-					0x3000)
+#define BL2_OFFSET			(0x5000)
 #else
 /* Put BL2 towards the middle of the Trusted SRAM */
-#define BL2_BASE			(ARM_TRUSTED_SRAM_BASE + \
-					(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
-					0x2000)
+#define BL2_OFFSET			(0x2000)
 #endif /* ENABLE_PIE */
+
+#define BL2_BASE			(ARM_TRUSTED_SRAM_BASE + \
+					    (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
+					    BL2_OFFSET)
 #define BL2_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 
 #else
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index e8461f5..2fdbfb7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -39,6 +39,20 @@
  *   - Region 1 with secure access only;
  *   - the remaining DRAM regions access from the given Non-Secure masters.
  ******************************************************************************/
+
+#if ENABLE_RME
+#define ARM_TZC_RME_REGIONS_DEF						    \
+	{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
+	{ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0},	    \
+	{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS,	    \
+		PLAT_ARM_TZC_NS_DEV_ACCESS},				    \
+	/* Realm and Shared area share the same PAS */		    \
+	{ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS,  \
+		PLAT_ARM_TZC_NS_DEV_ACCESS},				    \
+	{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS,	    \
+		PLAT_ARM_TZC_NS_DEV_ACCESS}
+#endif
+
 #if SPM_MM
 #define ARM_TZC_REGIONS_DEF						\
 	{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
@@ -52,16 +66,16 @@
 		PLAT_ARM_TZC_NS_DEV_ACCESS}
 
 #elif ENABLE_RME
-#define ARM_TZC_REGIONS_DEF						    \
-	{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
-	{ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0},	    \
-	{ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS,	    \
-		PLAT_ARM_TZC_NS_DEV_ACCESS},				    \
-	/* Realm and Shared area share the same PAS */		    \
-	{ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS,  \
-		PLAT_ARM_TZC_NS_DEV_ACCESS},				    \
-	{ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS,	    \
-		PLAT_ARM_TZC_NS_DEV_ACCESS}
+#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) &&  \
+MEASURED_BOOT
+#define ARM_TZC_REGIONS_DEF					        \
+	ARM_TZC_RME_REGIONS_DEF,					\
+	{ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END,             \
+		TZC_REGION_S_RDWR, 0}
+#else
+#define ARM_TZC_REGIONS_DEF					        \
+	ARM_TZC_RME_REGIONS_DEF
+#endif
 
 #else
 #define ARM_TZC_REGIONS_DEF						\
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index c781d38..98d148e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -42,6 +42,14 @@
 
 check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
 
+workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
+	/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+	sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
+	sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
+workaround_reset_end cortex_x3, ERRATUM(2742421)
+
+check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
+
 workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
 #if IMAGE_BL31
 	override_vector_table wa_cve_vbar_cortex_x3
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 88ef8a7..0d8f4d4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -742,6 +742,10 @@
 # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
 CPU_FLAG_LIST += ERRATA_X3_2615812
 
+# Flag to apply erratum 2742421 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2742421
+
 # Flag to apply erratum 1922240 workaround during reset. This erratum applies
 # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
 CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index a3351eb..3a2c53f 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -118,8 +118,10 @@
 ifeq (${NEED_BL32},yes)
     $(if ${BL32_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL32_KEY},--tos-fw-key)))
     $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert))
+ifneq (${COT},cca)
     $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert))
 endif
+endif
 
 # Add the BL33 CoT (key cert + img cert)
 ifneq (${BL33},)
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 777784d..4665827 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -52,8 +52,6 @@
 # Force generation of the new hash if ROT_KEY is specified
 ifdef ROT_KEY
 	HASH_PREREQUISITES = $(ROT_KEY) FORCE
-else
-	HASH_PREREQUISITES = $(ROT_KEY)
 endif
 
 $(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES)
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 534a175..51dda9e 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -65,25 +65,6 @@
 	/* Disable coherency if this cluster is to be turned off */
 	fvp_interconnect_disable();
 
-#if HW_ASSISTED_COHERENCY
-	uint32_t reg;
-
-	/*
-	 * If we have determined this core to be the last man standing and we
-	 * intend to power down the cluster proactively, we provide a hint to
-	 * the power controller that cluster power is not required when all
-	 * cores are powered down.
-	 * Note that this is only an advisory to power controller and is supported
-	 * by SoCs with DynamIQ Shared Units only.
-	 */
-	reg = read_clusterpwrdn();
-
-	/* Clear and set bit 0 : Cluster power not required */
-	reg &= ~DSU_CLUSTER_PWR_MASK;
-	reg |= DSU_CLUSTER_PWR_OFF;
-	write_clusterpwrdn(reg);
-#endif
-
 	/* Program the power controller to turn the cluster off */
 	fvp_pwrc_write_pcoffr(mpidr);
 }
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index df04617..826fca2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -168,8 +168,13 @@
 #  define MAX_XLAT_TABLES		6
 # endif
 #elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES		11
-# define MAX_XLAT_TABLES		5
+# if ENABLE_RME && defined(IMAGE_BL2)
+#  define PLAT_ARM_MMAP_ENTRIES		12
+#  define MAX_XLAT_TABLES		6
+# else
+#  define PLAT_ARM_MMAP_ENTRIES		11
+#  define MAX_XLAT_TABLES		5
+# endif /* (IMAGE_BL2 && ENABLE_RME) */
 #else
 # define PLAT_ARM_MMAP_ENTRIES		12
 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
@@ -437,7 +442,12 @@
 /*
  * Maximum size of Event Log buffer used in Measured Boot Event Log driver
  */
+#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
+/* Account for additional measurements of secure partitions and SPM. */
+#define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x800)
+#else
 #define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x400)
+#endif
 
 /*
  * Maximum size of Event Log buffer used for DRTM
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 3222226..bb64e73 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -131,28 +131,8 @@
 	plat_arm_gic_cpuif_disable();
 
 	/* Cluster is to be turned off, so disable coherency */
-	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+	if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
 		plat_arm_interconnect_exit_coherency();
-
-#if HW_ASSISTED_COHERENCY
-		uint32_t reg;
-
-		/*
-		 * If we have determined this core to be the last man standing and we
-		 * intend to power down the cluster proactively, we provide a hint to
-		 * the power controller that cluster power is not required when all
-		 * cores are powered down.
-		 * Note that this is only an advisory to power controller and is supported
-		 * by SoCs with DynamIQ Shared Units only.
-		 */
-		reg = read_clusterpwrdn();
-
-		/* Clear and set bit 0 : Cluster power not required */
-		reg &= ~DSU_CLUSTER_PWR_MASK;
-		reg |= DSU_CLUSTER_PWR_OFF;
-		write_clusterpwrdn(reg);
-#endif
-	}
 }
 
 /*******************************************************************************
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index b8b57d2..618e6c9 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -17,15 +17,29 @@
 else
 QEMU_CPU_LIBS		:=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
+				lib/cpus/aarch64/cortex_a55.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
 				lib/cpus/aarch64/cortex_a72.S		\
 				lib/cpus/aarch64/cortex_a76.S		\
+				lib/cpus/aarch64/cortex_a710.S		\
 				lib/cpus/aarch64/neoverse_n_common.S	\
 				lib/cpus/aarch64/neoverse_n1.S		\
 				lib/cpus/aarch64/neoverse_v1.S		\
 				lib/cpus/aarch64/qemu_max.S
 
 PLAT_INCLUDES		+=	-Iinclude/plat/arm/common/${ARCH}
+
+# Cpu core architecture level:
+# v8.0: a53, a57, a72
+# v8.2: a76, n1
+# v8.4: v1
+# v9.0: a710
+#
+# let treat v9.0 as v8.5 as they share cpu features
+# https://developer.arm.com/documentation/102378/0201/Armv8-x-and-Armv9-x-extensions-and-features
+
+ARM_ARCH_MAJOR		:=	8
+ARM_ARCH_MINOR		:=	5
 endif
 
 PLAT_BL_COMMON_SOURCES	:=	${PLAT_QEMU_COMMON_PATH}/qemu_common.c		\
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 012aaa6..911f664 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -8,6 +8,7 @@
 #include <common/fdt_fixup.h>
 #include <common/fdt_wrappers.h>
 #include <libfdt.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 #include <plat_fdt.h>
 #include <platform_def.h>
@@ -24,6 +25,17 @@
 	if (IS_TFA_IN_OCM(BL31_BASE))
 		return;
 
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+	ret = mmap_add_dynamic_region((unsigned long long)dtb,
+				      (uintptr_t)dtb,
+				      XILINX_OF_BOARD_DTB_MAX_SIZE,
+				      MT_MEMORY | MT_RW | MT_NS);
+	if (ret != 0) {
+		WARN("Failed to add dynamic region for dtb: error %d\n", ret);
+		return;
+	}
+#endif
+
 	/* Return if no device tree is detected */
 	if (fdt_check_header(dtb) != 0) {
 		NOTICE("Can't read DT at %p\n", dtb);
@@ -48,6 +60,16 @@
 		return;
 	}
 
-	clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+	flush_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+	ret = mmap_remove_dynamic_region((uintptr_t)dtb,
+					 XILINX_OF_BOARD_DTB_MAX_SIZE);
+	if (ret != 0) {
+		WARN("Failed to remove dynamic region for dtb: error %d\n", ret);
+		return;
+	}
+#endif
+
 	INFO("Changed device tree to advertise PSCI and reserved memories.\n");
 }
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 6cb529b..c50f06f 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -224,7 +224,8 @@
 	plat_arm_interconnect_enter_coherency();
 
 	const mmap_region_t bl_regions[] = {
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \
+	(!defined(PLAT_XLAT_TABLES_DYNAMIC)))
 		MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
 				MT_MEMORY | MT_RW | MT_NS),
 #endif
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index c936220..a052713 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -49,6 +49,11 @@
 $(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
 endif
 
+PLAT_XLAT_TABLES_DYNAMIC := 0
+ifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+endif
+
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iplat/xilinx/common/include/			\
 				-Iplat/xilinx/common/ipi_mailbox_service/	\
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 9906fac..e24a621 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -28,6 +28,7 @@
 #include <cortex_a715.h>
 #include <cortex_x1.h>
 #include <cortex_x2.h>
+#include <cortex_x3.h>
 #include <neoverse_n1.h>
 #include <neoverse_n2.h>
 #include <neoverse_v1.h>
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 5593516..8fee6ac 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -418,6 +418,18 @@
 	}
 },
 #endif /* CORTEX_A715_H_INC */
+
+#if CORTEX_X3_H_INC
+{
+	.cpu_partnumber = CORTEX_X3_MIDR,
+	.cpu_errata_list = {
+		[0] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
+		[1] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
+		[2] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
+		[3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+	}
+},
+#endif /* CORTEX_X3_H_INC */
 };
 
 /*