commit d594239d4ebf2d44521bc30ec4b59b23f08c5a36
author Lionel Debieve <lionel.debieve@foss.st.com> Wed Feb 23 00:05:51 2022 +0100
committer Yann Gautier <yann.gautier@st.com> Tue Jun 11 11:45:38 2024 +0200
tree 29383fd20ac84e1af62157d3edafe97468c2115b
parent caa1295779b479b49ef831c026e85feba03f3b19

feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation

LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee

fdts/stm32mp157a-avenger96.dts

diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index f0da350..ac8b162 100644
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -228,7 +228,7 @@
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q
 		CLK_SAI4_PLL3Q
-		CLK_RNG1_LSI
+		CLK_RNG1_CSI
 		CLK_RNG2_LSI
 		CLK_LPTIM1_PCLK1
 		CLK_LPTIM23_PCLK3