diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2788174..c6a5c08 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,24 +1,24 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <cortex_ares.h>
+#include <neoverse_n1.h>
 #include <cpuamu.h>
 #include <cpu_macros.S>
 
 /* --------------------------------------------------
- * Errata Workaround for Cortex-Ares Errata
- * This applies to revision r0p0 and r1p0 of Cortex-Ares.
+ * Errata Workaround for Neoverse N1 Errata
+ * This applies to revision r0p0 and r1p0 of Neoverse N1.
  * Inputs:
  * x0: variant[4:7] and revision[0:3] of current cpu.
  * Shall clobber: x0-x17
  * --------------------------------------------------
  */
-func errata_ares_1043202_wa
+func errata_n1_1043202_wa
 	/* Compare x0 against revision r1p0 */
 	mov	x17, x30
 	bl	check_errata_1043202
@@ -36,7 +36,7 @@
 	isb
 1:
 	ret	x17
-endfunc errata_ares_1043202_wa
+endfunc errata_n1_1043202_wa
 
 func check_errata_1043202
 	/* Applies to r0p0 and r1p0 */
@@ -44,58 +44,58 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_1043202
 
-func cortex_ares_reset_func
+func neoverse_n1_reset_func
 	mov	x19, x30
 	bl	cpu_get_rev_var
 	mov	x18, x0
 
-#if ERRATA_ARES_1043202
+#if ERRATA_N1_1043202
 	mov	x0, x18
-	bl	errata_ares_1043202_wa
+	bl	errata_n1_1043202_wa
 #endif
 
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
-	orr	x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT
+	orr	x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 	msr	actlr_el3, x0
 	isb
 
 	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
 	mrs	x0, actlr_el2
-	orr	x0, x0, #CORTEX_ARES_ACTLR_AMEN_BIT
+	orr	x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 	msr	actlr_el2, x0
 	isb
 
 	/* Enable group0 counters */
-	mov	x0, #CORTEX_ARES_AMU_GROUP0_MASK
+	mov	x0, #NEOVERSE_N1_AMU_GROUP0_MASK
 	msr	CPUAMCNTENSET_EL0, x0
 	isb
 #endif
 	ret	x19
-endfunc cortex_ares_reset_func
+endfunc neoverse_n1_reset_func
 
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
 	 */
-func cortex_ares_core_pwr_dwn
+func neoverse_n1_core_pwr_dwn
 	/* ---------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * ---------------------------------------------
 	 */
-	mrs	x0, CORTEX_ARES_CPUPWRCTLR_EL1
-	orr	x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
-	msr	CORTEX_ARES_CPUPWRCTLR_EL1, x0
+	mrs	x0, NEOVERSE_N1_CPUPWRCTLR_EL1
+	orr	x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
+	msr	NEOVERSE_N1_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_ares_core_pwr_dwn
+endfunc neoverse_n1_core_pwr_dwn
 
 #if REPORT_ERRATA
 /*
- * Errata printing function for Cortex-Ares. Must follow AAPCS.
+ * Errata printing function for Neoverse N1. Must follow AAPCS.
  */
-func cortex_ares_errata_report
+func neoverse_n1_errata_report
 	stp	x8, x30, [sp, #-16]!
 
 	bl	cpu_get_rev_var
@@ -105,15 +105,15 @@
 	 * Report all errata. The revision-variant information is passed to
 	 * checking functions of each errata.
 	 */
-	report_errata ERRATA_ARES_1043202, cortex_ares, 1043202
+	report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
 
 	ldp	x8, x30, [sp], #16
 	ret
-endfunc cortex_ares_errata_report
+endfunc neoverse_n1_errata_report
 #endif
 
 	/* ---------------------------------------------
-	 * This function provides cortex_ares specific
+	 * This function provides neoverse_n1 specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -121,16 +121,16 @@
 	 * reported.
 	 * ---------------------------------------------
 	 */
-.section .rodata.cortex_ares_regs, "aS"
-cortex_ares_regs:  /* The ascii list of register names to be reported */
+.section .rodata.neoverse_n1_regs, "aS"
+neoverse_n1_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_ares_cpu_reg_dump
-	adr	x6, cortex_ares_regs
-	mrs	x8, CORTEX_ARES_CPUECTLR_EL1
+func neoverse_n1_cpu_reg_dump
+	adr	x6, neoverse_n1_regs
+	mrs	x8, NEOVERSE_N1_CPUECTLR_EL1
 	ret
-endfunc cortex_ares_cpu_reg_dump
+endfunc neoverse_n1_cpu_reg_dump
 
-declare_cpu_ops cortex_ares, CORTEX_ARES_MIDR, \
-	cortex_ares_reset_func, \
-	cortex_ares_core_pwr_dwn
+declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \
+	neoverse_n1_reset_func, \
+	neoverse_n1_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c
index 4a4f333..b1b7bb8 100644
--- a/lib/cpus/aarch64/neoverse_n1_pubsub.c
+++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c
@@ -1,28 +1,28 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <cortex_ares.h>
+#include <neoverse_n1.h>
 #include <cpuamu.h>
 #include <lib/el3_runtime/pubsub_events.h>
 
-static void *cortex_ares_context_save(const void *arg)
+static void *neoverse_n1_context_save(const void *arg)
 {
-	if (midr_match(CORTEX_ARES_MIDR) != 0)
-		cpuamu_context_save(CORTEX_ARES_AMU_NR_COUNTERS);
+	if (midr_match(NEOVERSE_N1_MIDR) != 0)
+		cpuamu_context_save(NEOVERSE_N1_AMU_NR_COUNTERS);
 
 	return (void *)0;
 }
 
-static void *cortex_ares_context_restore(const void *arg)
+static void *neoverse_n1_context_restore(const void *arg)
 {
-	if (midr_match(CORTEX_ARES_MIDR) != 0)
-		cpuamu_context_restore(CORTEX_ARES_AMU_NR_COUNTERS);
+	if (midr_match(NEOVERSE_N1_MIDR) != 0)
+		cpuamu_context_restore(NEOVERSE_N1_AMU_NR_COUNTERS);
 
 	return (void *)0;
 }
 
-SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, cortex_ares_context_save);
-SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, cortex_ares_context_restore);
+SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, neoverse_n1_context_save);
+SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, neoverse_n1_context_restore);
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 40a8ac7..7824df2 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -120,8 +120,8 @@
 ERRATA_A72_859971	?=0
 
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
-# only to r0p0 and r1p0 of the Ares cpu.
-ERRATA_ARES_1043202	?=1
+# only to r0p0 and r1p0 of the Neoverse N1 cpu.
+ERRATA_N1_1043202	?=1
 
 # Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
 # the ACP interface and revision < r2p0. Applying the workaround results in
@@ -188,9 +188,9 @@
 $(eval $(call assert_boolean,ERRATA_A72_859971))
 $(eval $(call add_define,ERRATA_A72_859971))
 
-# Process ERRATA_ARES_1043202 flag
-$(eval $(call assert_boolean,ERRATA_ARES_1043202))
-$(eval $(call add_define,ERRATA_ARES_1043202))
+# Process ERRATA_N1_1043202 flag
+$(eval $(call assert_boolean,ERRATA_N1_1043202))
+$(eval $(call add_define,ERRATA_N1_1043202))
 
 # Process ERRATA_DSU_936184 flag
 $(eval $(call assert_boolean,ERRATA_DSU_936184))