Merge "feat(mt8196): fix MT8196 gpio driver" into integration
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
index 3f1fff2..46e5f67 100644
--- a/.github/dependabot.yml
+++ b/.github/dependabot.yml
@@ -36,13 +36,13 @@
- target-branch: "main"
package-ecosystem: "pip"
versioning-strategy: "lockfile-only"
- directories: ["/", "/tools/cot_dt2c", "/tools/tlc"]
+ directories: ["/", "/tools/cot_dt2c", "/tools/memory", "/tools/tlc"]
schedule:
interval: "daily"
groups:
dev-deps:
patterns: ["*"]
- update-types: ["major", "minor", "patch"]
+ update-types: ["minor", "patch"]
- target-branch: "lts-v2.10"
package-ecosystem: "pip"
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 2d1afab..d308fdd 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2023-2024, Arm Limited. All rights reserved
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,7 +20,7 @@
post_create_environment:
- pip install poetry=="1.3.2"
post_install:
- - VIRTUAL_ENV=$READTHEDOCS_VIRTUALENV_PATH poetry install --with docs
+ - VIRTUAL_ENV=$READTHEDOCS_VIRTUALENV_PATH poetry install --no-root --with docs
sphinx:
configuration: docs/conf.py
@@ -28,4 +28,3 @@
# Auxiliary formats to export to (in addition to the default HTML output).
formats:
- pdf
-
diff --git a/Makefile b/Makefile
index a3aad12..120ba5b 100644
--- a/Makefile
+++ b/Makefile
@@ -433,28 +433,12 @@
################################################################################
ifneq (${SPD},none)
- ifeq (${ARCH},aarch32)
- $(error "Error: SPD is incompatible with AArch32.")
- endif
-
- ifdef EL3_PAYLOAD_BASE
- $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
- $(warning "The SPD and its BL32 companion will be present but \
- ignored.")
- endif
-
ifeq (${SPD},spmd)
# SPMD is located in std_svc directory
SPD_DIR := std_svc
ifeq ($(SPMD_SPM_AT_SEL2),1)
CTX_INCLUDE_EL2_REGS := 1
- ifeq ($(SPMC_AT_EL3),1)
- $(error SPM cannot be enabled in both S-EL2 and EL3.)
- endif
- ifeq ($(CTX_INCLUDE_SVE_REGS),1)
- $(error SVE context management not needed with Hafnium SPMC.)
- endif
endif
ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
@@ -476,12 +460,6 @@
ifneq ($(SP_LAYOUT_FILE),)
BL2_ENABLE_SP_LOAD := 1
endif
-
- ifeq ($(SPMC_AT_EL3_SEL0_SP),1)
- ifneq ($(SPMC_AT_EL3),1)
- $(error SEL0 SP cannot be enabled without SPMC at EL3)
- endif
- endif
else
# All other SPDs in spd directory
SPD_DIR := spd
@@ -507,15 +485,6 @@
# over the sources.
endif #(SPD=none)
-ifeq (${ENABLE_SPMD_LP}, 1)
-ifneq (${SPD},spmd)
- $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
-endif
-ifeq ($(SPMC_AT_EL3),1)
- $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
-endif
-endif
-
################################################################################
# Include the platform specific Makefile after the SPD Makefile (the platform
# makefile may use all previous definitions in this file)
@@ -774,6 +743,42 @@
# Check incompatible options and dependencies
################################################################################
+# Handle all invalid build configurations with SPMD usage.
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq (${SPD},spmd)
+ $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
+endif
+ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
+endif
+endif
+
+ifneq (${SPD},none)
+ifeq (${ARCH},aarch32)
+ $(error "Error: SPD is incompatible with AArch32.")
+endif
+ifdef EL3_PAYLOAD_BASE
+ $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
+ $(warning "The SPD and its BL32 companion will be present but ignored.")
+endif
+ifeq (${SPD},spmd)
+ifeq ($(SPMD_SPM_AT_SEL2),1)
+ ifeq ($(SPMC_AT_EL3),1)
+ $(error SPM cannot be enabled in both S-EL2 and EL3.)
+ endif
+ ifeq ($(CTX_INCLUDE_SVE_REGS),1)
+ $(error SVE context management not needed with Hafnium SPMC.)
+ endif
+endif
+
+ifeq ($(SPMC_AT_EL3_SEL0_SP),1)
+ ifneq ($(SPMC_AT_EL3),1)
+ $(error SEL0 SP cannot be enabled without SPMC at EL3)
+ endif
+endif
+endif #(SPD=spmd)
+endif #(SPD!=none)
+
# USE_DEBUGFS experimental feature recommended only in debug builds
ifeq (${USE_DEBUGFS},1)
ifeq (${DEBUG},1)
@@ -1757,8 +1762,7 @@
$(q)${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} CRYPTO_SUPPORT=${CRYPTO_SUPPORT} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
memmap: all
- $(q)PYTHONPATH=${CURDIR}/tools/memory \
- ${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
+ $(q)$(if $(host-poetry),poetry run )memory -sr ${BUILD_PLAT}
tl: ${BUILD_PLAT}/tl.bin
${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 91ea75d..fce17e1 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -245,26 +245,30 @@
*/
func ea_proceed
/*
- * If the ESR loaded earlier is not zero, we were processing an EA
- * already, and this is a double fault.
+ * If it is a double fault invoke platform handler.
+ * Double fault scenario would arise when platform is handling a fault in
+ * lower EL using plat_ea_handler() and another fault happens which would
+ * trap into EL3 as FFH_SUPPORT is enabled for the platform.
*/
- ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
+ ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
cbz x5, 1f
no_ret plat_handle_double_fault
1:
- /* Save EL3 state */
+ /* Save EL3 state as handling might involve lower ELs */
mrs x2, spsr_el3
mrs x3, elr_el3
stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
+ mrs x4, scr_el3
+ str x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
/*
- * Save ESR as handling might involve lower ELs, and returning back to
- * EL3 from there would trample the original ESR.
+ * Save CTX_DOUBLE_FAULT_ESR, so that if another fault happens in lower EL, we
+ * catch it as DoubleFault in next invocation of ea_proceed() along with
+ * preserving original ESR_EL3.
*/
- mrs x4, scr_el3
mrs x5, esr_el3
- stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ str x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
/*
* Setup rest of arguments, and call platform External Abort handler.
@@ -305,23 +309,15 @@
/* Make SP point to context */
msr spsel, #MODE_SP_ELX
- /* Restore EL3 state and ESR */
+ /* Clear Double Fault storage */
+ str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
+
+ /* Restore EL3 state */
ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
msr spsr_el3, x1
msr elr_el3, x2
-
- /* Restore ESR_EL3 and SCR_EL3 */
- ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ ldr x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
msr scr_el3, x3
- msr esr_el3, x4
-
-#if ENABLE_ASSERTIONS
- cmp x4, xzr
- ASM_ASSERT(ne)
-#endif
-
- /* Clear ESR storage */
- str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
ret x29
endfunc ea_proceed
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 7914f6d..3e33824 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -387,7 +387,7 @@
Firmware Encryption Framework
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|M|: Sumit Garg <sumit.garg@kernel.org>
:|G|: `b49020`_
:|F|: drivers/io/io_encrypted.c
:|F|: include/drivers/io/io_encrypted.h
@@ -895,7 +895,7 @@
Synquacer platform port
^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|M|: Sumit Garg <sumit.garg@kernel.org>
:|G|: `b49020`_
:|M|: Masahisa Kojima <kojima.masahisa@socionext.com>
:|G|: `masahisak`_
@@ -996,7 +996,7 @@
Encrypt_fw tool
^^^^^^^^^^^^^^^
-:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|M|: Sumit Garg <sumit.garg@kernel.org>
:|G|: `b49020`_
:|F|: tools/encrypt_fw/
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 9ca2aa9..d06d153 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -1001,7 +1001,7 @@
This function returns the size normal-world DCE of the platform.
Function : plat_drtm_get_imp_def_dlme_region_size()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1012,7 +1012,7 @@
of the platform.
Function : plat_drtm_get_tcb_hash_table_size()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1021,8 +1021,18 @@
This function returns the size of TCB hash table of the platform.
+Function : plat_drtm_get_acpi_tables_region_size()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : uint64_t
+
+This function returns the size of ACPI tables region of the platform.
+
Function : plat_drtm_get_tcb_hash_features()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1033,6 +1043,17 @@
platform.
For more details see section 3.3 Table 6 of `DRTM`_ specification.
+Function : plat_drtm_get_dlme_img_auth_features()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : uint64_t
+
+This function returns the DLME image authentication features.
+For more details see section 3.3 Table 6 of `DRTM`_ specification.
+
Function : plat_drtm_validate_ns_region()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst
index 8874bd7..d9c358d 100644
--- a/docs/tools/memory-layout-tool.rst
+++ b/docs/tools/memory-layout-tool.rst
@@ -23,7 +23,7 @@
.. code:: shell
- poetry install --with memory
+ poetry install --no-root
#. Verify that the tool runs in the installed virtual environment
@@ -231,6 +231,6 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2025, Arm Limited. All rights reserved.*
.. _Poetry: https://python-poetry.org/docs/
diff --git a/fdts/stm32mp157a-dk1-sp_min-fw-config.dts b/fdts/stm32mp157a-dk1-sp_min-fw-config.dts
new file mode 100644
index 0000000..40164f3
--- /dev/null
+++ b/fdts/stm32mp157a-dk1-sp_min-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE 0x20000000 /* 512MB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp157a-dk1-sp_min.dts b/fdts/stm32mp157a-dk1-sp_min.dts
new file mode 100644
index 0000000..ac5c2af
--- /dev/null
+++ b/fdts/stm32mp157a-dk1-sp_min.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157A-DK1 Discovery Board (SP_MIN)";
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_CSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+};
diff --git a/fdts/stm32mp157c-dk2-sp_min-fw-config.dts b/fdts/stm32mp157c-dk2-sp_min-fw-config.dts
new file mode 100644
index 0000000..40164f3
--- /dev/null
+++ b/fdts/stm32mp157c-dk2-sp_min-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE 0x20000000 /* 512MB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp157c-dk2-sp_min.dts b/fdts/stm32mp157c-dk2-sp_min.dts
new file mode 100644
index 0000000..350cd34
--- /dev/null
+++ b/fdts/stm32mp157c-dk2-sp_min.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp157c-dk2.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C-DK2 Discovery Board (SP_MIN)";
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_CSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+};
diff --git a/fdts/stm32mp157c-ed1-sp_min-fw-config.dts b/fdts/stm32mp157c-ed1-sp_min-fw-config.dts
new file mode 100644
index 0000000..5aff97f
--- /dev/null
+++ b/fdts/stm32mp157c-ed1-sp_min-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE 0x40000000 /* 1GB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp157c-ed1-sp_min.dts b/fdts/stm32mp157c-ed1-sp_min.dts
new file mode 100644
index 0000000..85d4fb1
--- /dev/null
+++ b/fdts/stm32mp157c-ed1-sp_min.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#include "stm32mp157c-ed1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter (SP_MIN)";
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_CSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ st,clkdiv = <
+ DIV(DIV_MPU, 1)
+ DIV(DIV_AXI, 0)
+ DIV(DIV_MCU, 0)
+ DIV(DIV_APB1, 1)
+ DIV(DIV_APB2, 1)
+ DIV(DIV_APB3, 1)
+ DIV(DIV_APB4, 1)
+ DIV(DIV_APB5, 2)
+ DIV(DIV_MCO1, 0)
+ DIV(DIV_MCO2, 0)
+ >;
+};
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index fe5f464..dddfe3a 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
@@ -195,43 +195,13 @@
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
- CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
- CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
- CLK_DSI_DSIPLL
CLK_STGEN_HSE
- CLK_USBPHY_HSE
- CLK_SPI2S1_PLL3Q
- CLK_SPI2S23_PLL3Q
- CLK_SPI45_HSI
- CLK_SPI6_HSI
CLK_I2C46_HSI
- CLK_SDMMC3_PLL4P
- CLK_USBO_USBPHY
- CLK_ADC_CKPER
- CLK_CEC_LSE
- CLK_I2C12_HSI
- CLK_I2C35_HSI
- CLK_UART1_HSI
CLK_UART24_HSI
- CLK_UART35_HSI
- CLK_UART6_HSI
- CLK_UART78_HSI
- CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4R
- CLK_SAI1_PLL3Q
- CLK_SAI2_PLL3Q
- CLK_SAI3_PLL3Q
- CLK_SAI4_PLL3Q
- CLK_RNG1_CSI
- CLK_RNG2_LSI
- CLK_LPTIM1_PCLK1
- CLK_LPTIM23_PCLK3
- CLK_LPTIM45_LSE
>;
st,clkdiv = <
@@ -244,8 +214,6 @@
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
- DIV(DIV_MCO1, 0)
- DIV(DIV_MCO2, 0)
>;
st,pll_vco {
diff --git a/fdts/stm32mp157c-ev1-sp_min-fw-config.dts b/fdts/stm32mp157c-ev1-sp_min-fw-config.dts
new file mode 100644
index 0000000..5aff97f
--- /dev/null
+++ b/fdts/stm32mp157c-ev1-sp_min-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE 0x40000000 /* 1GB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp157c-ev1-sp_min.dts b/fdts/stm32mp157c-ev1-sp_min.dts
new file mode 100644
index 0000000..9513449
--- /dev/null
+++ b/fdts/stm32mp157c-ev1-sp_min.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
+ */
+/dts-v1/;
+
+#include "stm32mp157c-ed1-sp_min.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter on eval mother (SP_MIN)";
+ compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ aliases {
+ serial1 = &usart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&fmc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fmc_pins_a>;
+ status = "okay";
+
+ nand-controller@4,0 {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&usart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usart3_pins_b>;
+ uart-has-rtscts;
+ status = "disabled";
+};
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index 3115a00..1c7c4c3 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2019-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2025, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@@ -199,43 +199,11 @@
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
- CLK_MCO1_DISABLED
- CLK_MCO2_DISABLED
CLK_CKPER_HSE
- CLK_FMC_ACLK
- CLK_QSPI_ACLK
- CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
- CLK_DSI_DSIPLL
CLK_STGEN_HSE
- CLK_USBPHY_HSE
- CLK_SPI2S1_PLL3Q
- CLK_SPI2S23_PLL3Q
- CLK_SPI45_HSI
- CLK_SPI6_HSI
CLK_I2C46_HSI
- CLK_SDMMC3_PLL4P
- CLK_USBO_USBPHY
- CLK_ADC_CKPER
- CLK_CEC_LSE
- CLK_I2C12_HSI
- CLK_I2C35_HSI
- CLK_UART1_HSI
CLK_UART24_HSI
- CLK_UART35_HSI
- CLK_UART6_HSI
- CLK_UART78_HSI
- CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4R
- CLK_SAI1_PLL3Q
- CLK_SAI2_PLL3Q
- CLK_SAI3_PLL3Q
- CLK_SAI4_PLL3Q
- CLK_RNG1_CSI
- CLK_RNG2_LSI
- CLK_LPTIM1_PCLK1
- CLK_LPTIM23_PCLK3
- CLK_LPTIM45_LSE
>;
st,clkdiv = <
@@ -248,8 +216,6 @@
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
- DIV(DIV_MCO1, 0)
- DIV(DIV_MCO2, 0)
>;
st,pll_vco {
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 15d5204..d9a9188 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -67,25 +67,25 @@
******************************************************************************/
#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
#define CTX_SCR_EL3 U(0x0)
-#define CTX_ESR_EL3 U(0x8)
-#define CTX_RUNTIME_SP U(0x10)
-#define CTX_SPSR_EL3 U(0x18)
-#define CTX_ELR_EL3 U(0x20)
-#define CTX_PMCR_EL0 U(0x28)
-#define CTX_IS_IN_EL3 U(0x30)
-#define CTX_MDCR_EL3 U(0x38)
+#define CTX_RUNTIME_SP U(0x8)
+#define CTX_SPSR_EL3 U(0x10)
+#define CTX_ELR_EL3 U(0x18)
+#define CTX_PMCR_EL0 U(0x20)
+#define CTX_IS_IN_EL3 U(0x28)
+#define CTX_MDCR_EL3 U(0x30)
/* Constants required in supporting nested exception in EL3 */
-#define CTX_SAVED_ELR_EL3 U(0x40)
+#define CTX_SAVED_ELR_EL3 U(0x38)
/*
* General purpose flag, to save various EL3 states
* FFH mode : Used to identify if handling nested exception
* KFH mode : Used as counter value
*/
-#define CTX_NESTED_EA_FLAG U(0x48)
+#define CTX_NESTED_EA_FLAG U(0x40)
#if FFH_SUPPORT
- #define CTX_SAVED_ESR_EL3 U(0x50)
- #define CTX_SAVED_SPSR_EL3 U(0x58)
- #define CTX_SAVED_GPREG_LR U(0x60)
+ #define CTX_SAVED_ESR_EL3 U(0x48)
+ #define CTX_SAVED_SPSR_EL3 U(0x50)
+ #define CTX_SAVED_GPREG_LR U(0x58)
+ #define CTX_DOUBLE_FAULT_ESR U(0x60)
#define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */
#else
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index bcf9fc9..c403031 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h
@@ -110,6 +110,7 @@
CASSERT(sizeof(struct transfer_list_entry) == U(0x8), assert_transfer_list_entry_size);
+void transfer_entry_dump(struct transfer_list_entry *te);
void transfer_list_dump(struct transfer_list_header *tl);
struct transfer_list_header *transfer_list_ensure(void *addr, size_t size);
entry_point_info_t *
diff --git a/include/plat/common/plat_drtm.h b/include/plat/common/plat_drtm.h
index 07545a6..0d6a818 100644
--- a/include/plat/common/plat_drtm.h
+++ b/include/plat/common/plat_drtm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,6 +59,8 @@
uint64_t plat_drtm_get_tcb_hash_table_size(void);
uint64_t plat_drtm_get_imp_def_dlme_region_size(void);
uint64_t plat_drtm_get_tcb_hash_features(void);
+uint64_t plat_drtm_get_acpi_tables_region_size(void);
+uint64_t plat_drtm_get_dlme_img_auth_features(void);
/* DRTM error handling functions */
int plat_set_drtm_error(uint64_t error_code);
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index f0d3c63..3503fa4 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -49,6 +49,7 @@
#define ARM_DRTM_FEATURES_DMA_PROT U(0x3)
#define ARM_DRTM_FEATURES_BOOT_PE_ID U(0x4)
#define ARM_DRTM_FEATURES_TCB_HASHES U(0x5)
+#define ARM_DRTM_FEATURES_DLME_IMG_AUTH U(0x6)
#define is_drtm_fid(_fid) \
(((_fid) >= ARM_DRTM_SVC_VERSION) && ((_fid) <= ARM_DRTM_SVC_LOCK_TCB_HASH))
@@ -109,6 +110,9 @@
#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0)
#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF)
+#define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT U(0)
+#define ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK ULL(0x1)
+
#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \
do { \
reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
@@ -178,6 +182,16 @@
ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \
} while (false)
+#define ARM_DRTM_DLME_IMG_AUTH_SUPPORT(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK << \
+ ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)) | \
+ (((val) & \
+ ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_MASK) << \
+ ARM_DRTM_DLME_IMAGE_AUTH_SUPPORT_SHIFT)); \
+ } while (false)
+
/* Definitions for DRTM address map */
#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55)
#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3)
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 01a0395..71f4273 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -23,7 +23,14 @@
# Determine if mbedtls is needed
ifneq ($(filter $(CRYPTO_SUPPORT),1 2 3),)
PROCESSED_JMPTBL = $(BUILD_DIR)/jmptbl_processed.i
- $(shell mkdir -p $(BUILD_DIR) && cat ../../$(PLAT_DIR)/jmptbl.i ../../$(PLAT_DIR)/jmptbl_mbedtls.i > $(BUILD_DIR)/jmptbl_processed.i)
+ CRYPTO_JMPTBL = ../../$(PLAT_DIR)/jmptbl.i ../../$(PLAT_DIR)/jmptbl_mbedtls.i
+
+ ifeq (${PSA_CRYPTO},1)
+ CRYPTO_JMPTBL += ../../$(PLAT_DIR)/jmptbl_mbedtls_psa.i
+ endif # ifeq (${PSA_CRYPTO},1)
+
+ $(shell mkdir -p $(BUILD_DIR) && cat $(CRYPTO_JMPTBL) > $(PROCESSED_JMPTBL))
+
LIBS += $(LIB_DIR)/libmbedtls.a
endif
diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c
index 07614a6..3817861 100644
--- a/lib/transfer_list/transfer_list.c
+++ b/lib/transfer_list/transfer_list.c
@@ -35,7 +35,15 @@
if (!te) {
break;
}
+
INFO("Entry %d:\n", i++);
+ transfer_entry_dump(te);
+ }
+}
+
+void transfer_entry_dump(struct transfer_list_entry *te)
+{
+ if (te) {
INFO("tag_id 0x%x\n", te->tag_id);
INFO("hdr_size 0x%x\n", te->hdr_size);
INFO("data_size 0x%x\n", te->data_size);
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index 971dba4..bd7f017 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#include <arch_features.h>
#include <arch_helpers.h>
#include <common/debug.h>
+#include <lib/utils.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@@ -1204,16 +1205,13 @@
xlat_mmap_print(mm);
/* All tables must be zeroed before mapping any region. */
+ zeromem(ctx->base_table, ctx->base_table_entries * sizeof(uint64_t));
- for (unsigned int i = 0U; i < ctx->base_table_entries; i++)
- ctx->base_table[i] = INVALID_DESC;
-
- for (int j = 0; j < ctx->tables_num; j++) {
#if PLAT_XLAT_TABLES_DYNAMIC
- ctx->tables_mapped_regions[j] = 0;
+ zeromem(ctx->tables_mapped_regions, ctx->tables_num * sizeof(uint32_t));
#endif
- for (unsigned int i = 0U; i < XLAT_TABLE_ENTRIES; i++)
- ctx->tables[j][i] = INVALID_DESC;
+ for (int i = 0; i < ctx->tables_num; i++) {
+ zeromem(ctx->tables[i], XLAT_TABLE_ENTRIES * sizeof(uint64_t));
}
while (mm->size != 0U) {
diff --git a/plat/arm/board/fvp/fvp_drtm_stub.c b/plat/arm/board/fvp/fvp_drtm_stub.c
index e2bc516..238febd 100644
--- a/plat/arm/board/fvp/fvp_drtm_stub.c
+++ b/plat/arm/board/fvp/fvp_drtm_stub.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,3 +33,13 @@
{
return 0ULL;
}
+
+uint64_t plat_drtm_get_acpi_tables_region_size(void)
+{
+ return 0ULL;
+}
+
+uint64_t plat_drtm_get_dlme_img_auth_features(void)
+{
+ return 0ULL;
+}
diff --git a/plat/arm/board/fvp/jmptbl_mbedtls_psa.i b/plat/arm/board/fvp/jmptbl_mbedtls_psa.i
new file mode 100644
index 0000000..4eb707b
--- /dev/null
+++ b/plat/arm/board/fvp/jmptbl_mbedtls_psa.i
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform-specific ROMLIB MbedTLS PSA Crypto functions can be added here.
+# During the build process, this file is appended to jmptbl.i
+# if MbedTLS support is required and PSA Crypto is supported.
+#
+# Format:
+# lib function [patch]
+# Example:
+# mbedtls psa_crypto_init
+
+mbedtls mbedtls_pk_get_psa_attributes
+mbedtls mbedtls_pk_import_into_psa
+mbedtls psa_crypto_init
+mbedtls psa_destroy_key
+mbedtls psa_verify_message
diff --git a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
index dcee92c..19fb796 100644
--- a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
+++ b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
@@ -129,8 +129,7 @@
cpu_info->ErrCtxEl3Reg[0] = read_ctx_reg(get_el3state_ctx(ctx),
CTX_ELR_EL3);
- cpu_info->ErrCtxEl3Reg[1] = read_ctx_reg(get_el3state_ctx(ctx),
- CTX_ESR_EL3);
+ cpu_info->ErrCtxEl3Reg[1] = read_esr_el3();
cpu_info->ErrCtxEl3Reg[2] = read_far_el3();
cpu_info->ErrCtxEl3Reg[4] = read_mair_el3();
cpu_info->ErrCtxEl3Reg[5] = read_sctlr_el3();
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 245d930..1ddd0e4 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -144,7 +144,7 @@
${RDV3_BASE}/fdts/${PLAT}_nt_fw_config.dts
ifeq (${SPMD_SPM_AT_SEL2}, 1)
-BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts
+BL32_CONFIG_DTS := ${RDV3_BASE}/fdts/${PLAT}_spmc_sp_manifest.dts
FDT_SOURCES += ${BL32_CONFIG_DTS}
TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${BL32_CONFIG_DTS})).dtb
endif
@@ -169,4 +169,14 @@
# FEAT_SVE related flags
override SVE_VECTOR_LEN := 128
-override CTX_INCLUDE_SVE_REGS := 1
+
+override CTX_INCLUDE_SVE_REGS := 1
+
+# Enabling CTX_INCLUDE_SVE_REGS along with SPMD_SPM_AT_SEL2=1 is a invalid
+# combination and will lead to build failure, use them only when SPMD_SPM_AT_SEL2=0
+# In this combination its SPMC responsbility to save SVE regs.
+ifeq (${SPD},spmd)
+ifeq (${SPMD_SPM_AT_SEL2},1)
+override CTX_INCLUDE_SVE_REGS := 0
+endif
+endif
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 690507e..88c1087 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -41,7 +41,7 @@
# Create DTB file for BL2
${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | $$(@D)/
- $(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ $(q)echo '#include "$(patsubst %.dts,%$(SP_EXT).dts,$(patsubst fdts/%,%,$<))"' > $@
$(q)echo '#include "${BL2_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl2.dtb: ${BUILD_PLAT}/fdts/%-bl2.dts
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 3d37738..e700823 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -105,6 +105,11 @@
ifeq ($(AARCH32_SP),sp_min)
BL32_DTSI := stm32mp15-bl32.dtsi
FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
+ifneq (,$(wildcard $(patsubst %.dtb,fdts/%-sp_min.dts,$(DTB_FILE_NAME))))
+ifeq (,$(findstring -sp_min,$(DTB_FILE_NAME)))
+SP_EXT := -sp_min
+endif
+endif
endif
endif
@@ -258,7 +263,7 @@
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/
- $(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ $(q)echo '#include "$(patsubst %.dts,%$(SP_EXT).dts,$(patsubst fdts/%,%,$<))"' > $@
$(q)echo '#include "${BL32_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts | $$(@D)/
diff --git a/plat/st/stm32mp2/include/platform_def.h b/plat/st/stm32mp2/include/platform_def.h
index e720c02..523f9bb 100644
--- a/plat/st/stm32mp2/include/platform_def.h
+++ b/plat/st/stm32mp2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -73,8 +73,15 @@
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
+#if ENABLE_PIE
#define BL31_BASE 0
-#define BL31_LIMIT (STM32MP_SEC_SYSRAM_SIZE / 2)
+#else
+#define BL31_BASE STM32MP_SYSRAM_BASE
+#endif
+
+#define BL31_LIMIT (BL31_BASE + (STM32MP_SYSRAM_SIZE / 2))
+
+#define BL31_PROGBITS_LIMIT (BL31_BASE + STM32MP_BL31_SIZE)
/*******************************************************************************
* BL33 specific defines.
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index a9f8d8f..d5e2785 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -11,9 +11,12 @@
include plat/st/common/common.mk
CRASH_REPORTING := 1
-ENABLE_PIE := 1
+# Disable PIE by default. To re-enable it, uncomment next line.
+#ENABLE_PIE := 1
PROGRAMMABLE_RESET_ADDRESS := 1
+ifeq ($(ENABLE_PIE),1)
BL2_IN_XIP_MEM := 1
+endif
STM32MP_BL33_EL1 ?= 1
ifeq ($(STM32MP_BL33_EL1),1)
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index b441502..3e60cad 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -76,8 +76,6 @@
#define RETRAM_BASE U(0x0E080000)
#define RETRAM_SIZE U(0x00020000)
-#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
-
/* DDR configuration */
#define STM32MP_DDR_BASE U(0x80000000)
#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
@@ -113,11 +111,9 @@
#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
/* Allocate remaining sysram to BL31 Binary only */
-#define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
+#define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
-#define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
-
#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
diff --git a/poetry.lock b/poetry.lock
index 4127bcd..341a2bd 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.8.5 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.8.4 and should not be changed by hand.
[[package]]
name = "alabaster"
@@ -538,6 +538,25 @@
]
[[package]]
+name = "memory"
+version = "0.1.0"
+description = "A tool for analysis of "
+optional = false
+python-versions = "^3.8.0"
+files = []
+develop = true
+
+[package.dependencies]
+anytree = "^2.8.0"
+click = "^8.1.3"
+prettytable = "^3.5.0"
+pyelftools = "^0.29.0"
+
+[package.source]
+type = "directory"
+url = "tools/memory"
+
+[[package]]
name = "myst-parser"
version = "0.18.1"
description = "An extended commonmark compliant parser, with bridges to docutils & sphinx."
@@ -1147,7 +1166,7 @@
[package.dependencies]
click = "^8.1.7"
-jinja2 = "^3.1.4"
+jinja2 = "^3.1.5"
pyyaml = "^6.0.1"
rich = "^10.14.0"
tox = "^4.18.0"
@@ -1312,4 +1331,4 @@
[metadata]
lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "6a6d2fe9390a4d7d1ecf808d5f303f2dc1eeb44736827b706a858046f3eea1db"
+content-hash = "7574eee0a05db1d9631bb29288abfc806810906a66e087a5a32e6e3920eb4bba"
diff --git a/pyproject.toml b/pyproject.toml
index 62878b4..55f3f2a 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -5,16 +5,11 @@
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
readme = "readme.rst"
-packages = [
- { include = "memory", from = "tools/memory"}
-]
-
-[tool.poetry.scripts]
-memory = "memory.memmap:main"
[tool.poetry.dependencies]
python = "^3.8"
cot-dt2c = {path = "tools/cot_dt2c", develop = true}
+memory = {path = "tools/memory", develop = true}
tlc = {path = "tools/tlc", develop = true}
[tool.poetry.group.docs]
@@ -30,9 +25,3 @@
[tool.poetry.group.ci.dependencies]
click = "^8.1.3"
-
-[tool.poetry.group.memory.dependencies]
-pyelftools = "^0.29"
-anytree = "^2.8.0"
-click = "^8.1.3"
-prettytable = "^3.5.0"
diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index 37f2a2f..117934f 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c
@@ -104,12 +104,16 @@
dlme_data_hdr_init.dlme_addr_map_size = drtm_get_address_map_size();
dlme_data_hdr_init.dlme_tcb_hashes_table_size =
plat_drtm_get_tcb_hash_table_size();
+ dlme_data_hdr_init.dlme_acpi_tables_region_size =
+ plat_drtm_get_acpi_tables_region_size();
dlme_data_hdr_init.dlme_impdef_region_size =
plat_drtm_get_imp_def_dlme_region_size();
- dlme_data_min_size += dlme_data_hdr_init.dlme_addr_map_size +
+ dlme_data_min_size += sizeof(struct_dlme_data_header) +
+ dlme_data_hdr_init.dlme_addr_map_size +
ARM_DRTM_MIN_EVENT_LOG_SIZE +
dlme_data_hdr_init.dlme_tcb_hashes_table_size +
+ dlme_data_hdr_init.dlme_acpi_tables_region_size +
dlme_data_hdr_init.dlme_impdef_region_size;
/* Fill out platform DRTM features structure */
@@ -130,6 +134,8 @@
plat_dma_prot_feat->dma_protection_support);
ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(plat_drtm_features.tcb_hash_features,
plat_drtm_get_tcb_hash_features());
+ ARM_DRTM_DLME_IMG_AUTH_SUPPORT(plat_drtm_features.dlme_image_auth_features,
+ plat_drtm_get_dlme_img_auth_features());
return 0;
}
@@ -171,6 +177,12 @@
plat_drtm_features.tcb_hash_features);
}
+static inline uint64_t drtm_features_dlme_img_auth_features(void *ctx)
+{
+ SMC_RET2(ctx, 1ULL, /* DLME Image auth is supported */
+ plat_drtm_features.dlme_image_auth_features);
+}
+
static enum drtm_retc drtm_dl_check_caller_el(void *ctx)
{
uint64_t spsr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3);
@@ -785,6 +797,12 @@
return drtm_features_tcb_hashes(handle);
break; /* not reached */
+ case ARM_DRTM_FEATURES_DLME_IMG_AUTH:
+ INFO("++ DRTM service handler: "
+ "DLME Image authentication features\n");
+ return drtm_features_dlme_img_auth_features(handle);
+ break; /* not reached */
+
default:
ERROR("Unknown ARM DRTM service feature\n");
SMC_RET1(handle, NOT_SUPPORTED);
diff --git a/services/std_svc/drtm/drtm_main.h b/services/std_svc/drtm/drtm_main.h
index c105b56..44d0d2d 100644
--- a/services/std_svc/drtm/drtm_main.h
+++ b/services/std_svc/drtm/drtm_main.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -45,7 +45,7 @@
* Range(Min/Max) of DRTM parameter structure versions supported
*/
#define ARM_DRTM_PARAMS_MIN_VERSION U(1)
-#define ARM_DRTM_PARAMS_MAX_VERSION U(1)
+#define ARM_DRTM_PARAMS_MAX_VERSION U(2)
enum drtm_dlme_el {
DLME_AT_EL1 = MODE_EL1,
@@ -74,6 +74,7 @@
uint64_t dma_prot_features;
uint64_t boot_pe_id;
uint64_t tcb_hash_features;
+ uint64_t dlme_image_auth_features;
} drtm_features_t;
struct __packed drtm_dl_args_v1 {
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index 8d514b7..d4f2b57 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -198,6 +198,10 @@
PCR_18);
CHECK_RC(rc,
drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
+
+ /* Measure no Action event but not extend it in PCR */
+ CHECK_RC(rc,
+ drtm_event_log_measure_and_record(DRTM_EVENT_ARM_NO_ACTION));
/*
* If the DCE is unable to log a measurement because there is no available
* space in the event log region, the DCE must extend a hash of the value
diff --git a/services/std_svc/drtm/drtm_measurements.h b/services/std_svc/drtm/drtm_measurements.h
index 6d7a84e..f5a8c7c 100644
--- a/services/std_svc/drtm/drtm_measurements.h
+++ b/services/std_svc/drtm/drtm_measurements.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -25,6 +25,9 @@
#define DRTM_EVENT_ARM_DCE_SECONDARY DRTM_EVENT_TYPE(8)
#define DRTM_EVENT_ARM_TZFW DRTM_EVENT_TYPE(9)
#define DRTM_EVENT_ARM_SEPARATOR DRTM_EVENT_TYPE(10)
+#define DRTM_EVENT_ARM_DLME_PUBKEY DRTM_EVENT_TYPE(11)
+#define DRTM_EVENT_ARM_DLME_SVN DRTM_EVENT_TYPE(12)
+#define DRTM_EVENT_ARM_NO_ACTION DRTM_EVENT_TYPE(13)
#define CHECK_RC(rc, func_call) { \
if (rc != 0) { \
diff --git a/tools/memory/__init__.py b/tools/memory/__init__.py
deleted file mode 100644
index 0b4c8d3..0000000
--- a/tools/memory/__init__.py
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/usr/bin/env python3
-
-#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
diff --git a/tools/memory/memory/__init__.py b/tools/memory/memory/__init__.py
deleted file mode 100644
index 0b4c8d3..0000000
--- a/tools/memory/memory/__init__.py
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/usr/bin/env python3
-
-#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
diff --git a/tools/memory/poetry.lock b/tools/memory/poetry.lock
new file mode 100644
index 0000000..2747479
--- /dev/null
+++ b/tools/memory/poetry.lock
@@ -0,0 +1,95 @@
+# This file is automatically @generated by Poetry 1.8.4 and should not be changed by hand.
+
+[[package]]
+name = "anytree"
+version = "2.12.1"
+description = "Powerful and Lightweight Python Tree Data Structure with various plugins"
+optional = false
+python-versions = ">=3.7.2,<4"
+files = [
+ {file = "anytree-2.12.1-py3-none-any.whl", hash = "sha256:5ea9e61caf96db1e5b3d0a914378d2cd83c269dfce1fb8242ce96589fa3382f0"},
+ {file = "anytree-2.12.1.tar.gz", hash = "sha256:244def434ccf31b668ed282954e5d315b4e066c4940b94aff4a7962d85947830"},
+]
+
+[package.dependencies]
+six = "*"
+
+[[package]]
+name = "click"
+version = "8.1.8"
+description = "Composable command line interface toolkit"
+optional = false
+python-versions = ">=3.7"
+files = [
+ {file = "click-8.1.8-py3-none-any.whl", hash = "sha256:63c132bbbed01578a06712a2d1f497bb62d9c1c0d329b7903a866228027263b2"},
+ {file = "click-8.1.8.tar.gz", hash = "sha256:ed53c9d8990d83c2a27deae68e4ee337473f6330c040a31d4225c9574d16096a"},
+]
+
+[package.dependencies]
+colorama = {version = "*", markers = "platform_system == \"Windows\""}
+
+[[package]]
+name = "colorama"
+version = "0.4.6"
+description = "Cross-platform colored terminal text."
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
+files = [
+ {file = "colorama-0.4.6-py2.py3-none-any.whl", hash = "sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6"},
+ {file = "colorama-0.4.6.tar.gz", hash = "sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44"},
+]
+
+[[package]]
+name = "prettytable"
+version = "3.11.0"
+description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
+optional = false
+python-versions = ">=3.8"
+files = [
+ {file = "prettytable-3.11.0-py3-none-any.whl", hash = "sha256:aa17083feb6c71da11a68b2c213b04675c4af4ce9c541762632ca3f2cb3546dd"},
+ {file = "prettytable-3.11.0.tar.gz", hash = "sha256:7e23ca1e68bbfd06ba8de98bf553bf3493264c96d5e8a615c0471025deeba722"},
+]
+
+[package.dependencies]
+wcwidth = "*"
+
+[package.extras]
+tests = ["pytest", "pytest-cov", "pytest-lazy-fixtures"]
+
+[[package]]
+name = "pyelftools"
+version = "0.29"
+description = "Library for analyzing ELF files and DWARF debugging information"
+optional = false
+python-versions = "*"
+files = [
+ {file = "pyelftools-0.29-py2.py3-none-any.whl", hash = "sha256:519f38cf412f073b2d7393aa4682b0190fa901f7c3fa0bff2b82d537690c7fc1"},
+ {file = "pyelftools-0.29.tar.gz", hash = "sha256:ec761596aafa16e282a31de188737e5485552469ac63b60cfcccf22263fd24ff"},
+]
+
+[[package]]
+name = "six"
+version = "1.17.0"
+description = "Python 2 and 3 compatibility utilities"
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,>=2.7"
+files = [
+ {file = "six-1.17.0-py2.py3-none-any.whl", hash = "sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274"},
+ {file = "six-1.17.0.tar.gz", hash = "sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81"},
+]
+
+[[package]]
+name = "wcwidth"
+version = "0.2.13"
+description = "Measures the displayed width of unicode strings in a terminal"
+optional = false
+python-versions = "*"
+files = [
+ {file = "wcwidth-0.2.13-py2.py3-none-any.whl", hash = "sha256:3da69048e4540d84af32131829ff948f1e022c1c6bdb8d6102117aac784f6859"},
+ {file = "wcwidth-0.2.13.tar.gz", hash = "sha256:72ea0c06399eb286d978fdedb6923a9eb47e1c486ce63e9b4e64fc18303972b5"},
+]
+
+[metadata]
+lock-version = "2.0"
+python-versions = "^3.8.0"
+content-hash = "d7c185b3dbfc9bba145f12146e18ce501caf081d7762f138bc5a7fde99f40543"
diff --git a/tools/memory/pyproject.toml b/tools/memory/pyproject.toml
new file mode 100644
index 0000000..c2fdfcb
--- /dev/null
+++ b/tools/memory/pyproject.toml
@@ -0,0 +1,21 @@
+[tool.poetry]
+name = "memory"
+version = "0.1.0"
+description = "A tool for analysis of static memory consumption by TF-A images"
+authors = ["Chris Kay <chris.kay@arm.com>", "Harrison Mutai <harrison.mutai@arm.com>"]
+license = "BSD-3-Clause"
+packages = [{include = "memory", from = "src"}]
+
+[tool.poetry.dependencies]
+anytree = "^2.8.0"
+click = "^8.1.3"
+prettytable = "^3.5.0"
+pyelftools = "^0.29.0"
+python = "^3.8.0"
+
+[tool.poetry.scripts]
+memory = "memory.memmap:main"
+
+[build-system]
+requires = ["poetry-core"]
+build-backend = "poetry.core.masonry.api"
diff --git a/tools/memory/src/memory/__init__.py b/tools/memory/src/memory/__init__.py
new file mode 100644
index 0000000..8e0db6b
--- /dev/null
+++ b/tools/memory/src/memory/__init__.py
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/tools/memory/memory/buildparser.py b/tools/memory/src/memory/buildparser.py
similarity index 97%
rename from tools/memory/memory/buildparser.py
rename to tools/memory/src/memory/buildparser.py
index dedff79..ea417e1 100755
--- a/tools/memory/memory/buildparser.py
+++ b/tools/memory/src/memory/buildparser.py
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/tools/memory/memory/elfparser.py b/tools/memory/src/memory/elfparser.py
similarity index 98%
rename from tools/memory/memory/elfparser.py
rename to tools/memory/src/memory/elfparser.py
index 2dd2513..e6581c9 100644
--- a/tools/memory/memory/elfparser.py
+++ b/tools/memory/src/memory/elfparser.py
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/tools/memory/memory/mapparser.py b/tools/memory/src/memory/mapparser.py
similarity index 97%
rename from tools/memory/memory/mapparser.py
rename to tools/memory/src/memory/mapparser.py
index ce4cc31..1c28e71 100644
--- a/tools/memory/memory/mapparser.py
+++ b/tools/memory/src/memory/mapparser.py
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/tools/memory/memory/memmap.py b/tools/memory/src/memory/memmap.py
similarity index 97%
rename from tools/memory/memory/memmap.py
rename to tools/memory/src/memory/memmap.py
index 34f5069..f46db8c 100755
--- a/tools/memory/memory/memmap.py
+++ b/tools/memory/src/memory/memmap.py
@@ -1,7 +1,7 @@
#!/usr/bin/env python3
#
-# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/tools/memory/memory/printer.py b/tools/memory/src/memory/printer.py
similarity index 98%
rename from tools/memory/memory/printer.py
rename to tools/memory/src/memory/printer.py
index 4b18560..f797139 100755
--- a/tools/memory/memory/printer.py
+++ b/tools/memory/src/memory/printer.py
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#