diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 9ebca23..1506714 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -72,7 +72,8 @@
 ifeq (${RAS_FFH_SUPPORT},1)
 BL31_SOURCES		+=	${RDN2_BASE}/rdn2_ras.c			\
 				${CSS_ENT_BASE}/ras/sgi_ras_common.c	\
-				${CSS_ENT_BASE}/ras/sgi_ras_sram.c
+				${CSS_ENT_BASE}/ras/sgi_ras_sram.c	\
+				${CSS_ENT_BASE}/ras/sgi_ras_cpu.c
 endif
 
 # Add the FDT_SOURCES and options for Dynamic Config
diff --git a/plat/arm/board/rdn2/rdn2_ras.c b/plat/arm/board/rdn2/rdn2_ras.c
index c1e5ab6..3aed58e 100644
--- a/plat/arm/board/rdn2/rdn2_ras.c
+++ b/plat/arm/board/rdn2/rdn2_ras.c
@@ -14,6 +14,9 @@
 
 	/* Non Secure base RAM ECC UE interrupt */
 	{SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI},
+
+	/* CPU 1-bit ECC CE error interrupt */
+	{SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI}
 };
 
 /* RAS error record list definition, used by the common RAS framework. */
@@ -21,11 +24,15 @@
 	/* Base element RAM Non-secure error record. */
 	ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
 				&sgi_ras_sram_intr_handler, 0),
+	ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0),
 };
 
 /* RAS error interrupt list definition, used by the common RAS framework. */
 struct ras_interrupt plat_ras_interrupts[] = {
 	{
+		.intr_number = PLAT_CORE_FAULT_IRQ,
+		.err_record = &plat_err_records[1],
+	}, {
 		.intr_number = NS_RAM_ECC_CE_INT,
 		.err_record = &plat_err_records[0],
 	}, {