plat: imx8m: refactor the code to make it reusable
for the i.MX8M SOCs, part of the code for gpc
and PSCI implementation can be reused and make it
common for all these SoCs. this patch extracts
the common part for reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index ee58865..04e191f 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -13,55 +13,9 @@
#include <lib/psci/psci.h>
#include <gpc.h>
+#include <imx8m_psci.h>
#include <plat_imx8.h>
-#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
-#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
-#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
-
-int imx_pwr_domain_on(u_register_t mpidr)
-{
- unsigned int core_id;
- uint64_t base_addr = BL31_BASE;
-
- core_id = MPIDR_AFFLVL0_VAL(mpidr);
-
- /* set the secure entrypoint */
- imx_set_cpu_secure_entry(core_id, base_addr);
- /* power up the core */
- imx_set_cpu_pwr_on(core_id);
-
- return PSCI_E_SUCCESS;
-}
-
-void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- /* program the GIC per cpu dist and rdist interface */
- plat_gic_pcpu_init();
- /* enable the GICv3 cpu interface */
- plat_gic_cpuif_enable();
-}
-
-void imx_pwr_domain_off(const psci_power_state_t *target_state)
-{
- uint64_t mpidr = read_mpidr_el1();
- unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
-
- /* disable the GIC cpu interface first */
- plat_gic_cpuif_disable();
- /* config the core for power down */
- imx_set_cpu_pwr_off(core_id);
-}
-
-int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
-{
- /* The non-secure entrypoint should be in RAM space */
- if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET)
- return PSCI_E_INVALID_PARAMS;
-
- return PSCI_E_SUCCESS;
-}
-
int imx_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
@@ -85,18 +39,6 @@
return PSCI_E_SUCCESS;
}
-void imx_cpu_standby(plat_local_state_t cpu_state)
-{
- dsb();
- write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
- isb();
-
- wfi();
-
- write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
- isb();
-}
-
void imx_domain_suspend(const psci_power_state_t *target_state)
{
uint64_t base_addr = BL31_BASE;
@@ -120,7 +62,7 @@
imx_set_cluster_standby(true);
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
- imx_set_sys_lpm(true);
+ imx_set_sys_lpm(core_id, true);
}
}
@@ -131,7 +73,7 @@
/* check the system level status */
if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
- imx_set_sys_lpm(false);
+ imx_set_sys_lpm(core_id, false);
imx_clear_rbc_count();
}
@@ -163,47 +105,6 @@
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
}
-void __dead2 imx_system_reset(void)
-{
- uintptr_t wdog_base = IMX_WDOG_BASE;
- unsigned int val;
-
- /* WDOG_B reset */
- val = mmio_read_16(wdog_base);
-#ifdef IMX_WDOG_B_RESET
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
- WDOG_WCR_WDT | WDOG_WCR_SRS;
-#else
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
-#endif
- mmio_write_16(wdog_base, val);
-
- mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
- mmio_write_16(wdog_base + WDOG_WSR, 0xaaaa);
- while (1)
- ;
-}
-
-
-
-void __dead2 imx_system_off(void)
-{
- mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
- SNVS_LPCR_DP_EN | SNVS_LPCR_TOP);
-
- while (1)
- ;
-}
-
-void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
-{
- if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
- imx_set_rbc_count();
-
- while (1)
- wfi();
-}
-
static const plat_psci_ops_t imx_plat_psci_ops = {
.pwr_domain_on = imx_pwr_domain_on,
.pwr_domain_on_finish = imx_pwr_domain_on_finish,