Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" into integration
diff --git a/Makefile b/Makefile
index 1078ef5..ef3b042 100644
--- a/Makefile
+++ b/Makefile
@@ -220,23 +220,19 @@
ASFLAGS_aarch64 = $(march64-directive)
WARNING1 := -Wextra
-WARNING1 += -Wunused -Wno-unused-parameter
WARNING1 += -Wmissing-declarations
WARNING1 += -Wmissing-format-attribute
WARNING1 += -Wmissing-prototypes
WARNING1 += -Wold-style-definition
-WARNING1 += -Wunused-but-set-variable
WARNING1 += -Wunused-const-variable
WARNING2 := -Waggregate-return
WARNING2 += -Wcast-align
-WARNING2 += -Wdisabled-optimization
WARNING2 += -Wnested-externs
WARNING2 += -Wshadow
WARNING2 += -Wlogical-op
WARNING2 += -Wmissing-field-initializers
WARNING2 += -Wsign-compare
-WARNING2 += -Wmaybe-uninitialized
WARNING3 := -Wbad-function-cast
WARNING3 += -Wcast-qual
@@ -246,8 +242,6 @@
WARNING3 += -Wpointer-arith
WARNING3 += -Wredundant-decls
WARNING3 += -Wswitch-default
-WARNING3 += -Wpacked-bitfield-compat
-WARNING3 += -Wvla
ifeq (${W},1)
WARNINGS := $(WARNING1)
@@ -257,6 +251,16 @@
WARNINGS := $(WARNING1) $(WARNING2) $(WARNING3)
endif
+WARNINGS += -Wunused -Wno-unused-parameter \
+ -Wdisabled-optimization \
+ -Wvla
+
+ifeq ($(findstring clang,$(notdir $(CC))),)
+WARNINGS += -Wunused-but-set-variable \
+ -Wmaybe-uninitialized \
+ -Wpacked-bitfield-compat
+endif
+
ifneq (${E},0)
ERRORS := -Werror
endif
@@ -941,11 +945,13 @@
${Q}cscope -b -q -k
help:
- @echo "usage: ${MAKE} PLAT=<${PLATFORM_LIST}> [OPTIONS] [TARGET]"
+ @echo "usage: ${MAKE} [PLAT=<platform>] [OPTIONS] [TARGET]"
@echo ""
@echo "PLAT is used to specify which platform you wish to build."
@echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
@echo ""
+ @echo "platform = ${PLATFORM_LIST}"
+ @echo ""
@echo "Please refer to the User Guide for a list of all supported options."
@echo "Note that the build system doesn't track dependencies for build "
@echo "options. Therefore, if any of the build options are changed "
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index e49c73e..07983a9 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -143,6 +143,9 @@
- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
+- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
+ CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+
For Cortex-A57, the following errata build flags are defined :
- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h
index feac1d2..60ed957 100644
--- a/include/lib/cpus/aarch64/cortex_a55.h
+++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -39,4 +39,10 @@
/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
+/* Instruction patching registers */
+#define CPUPSELR_EL3 S3_6_C15_C8_0
+#define CPUPCR_EL3 S3_6_C15_C8_1
+#define CPUPOR_EL3 S3_6_C15_C8_2
+#define CPUPMR_EL3 S3_6_C15_C8_3
+
#endif /* CORTEX_A55_H */
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 0ef373a..8e13824 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -175,6 +175,53 @@
b cpu_rev_var_ls
endfunc check_errata_903758
+ /* -----------------------------------------------------
+ * Errata Workaround for Cortex A55 Errata #1221012.
+ * This applies only to revisions <= r1p0 of Cortex A55.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -----------------------------------------------------
+ */
+func errata_a55_1221012_wa
+ /*
+ * Compare x0 against revision r1p0
+ */
+ mov x17, x30
+ bl check_errata_1221012
+ cbz x0, 1f
+ mov x0, #0x0020
+ movk x0, #0x0850, lsl #16
+ msr CPUPOR_EL3, x0
+ mov x0, #0x0000
+ movk x0, #0x1FF0, lsl #16
+ movk x0, #0x2, lsl #32
+ msr CPUPMR_EL3, x0
+ mov x0, #0x03fd
+ movk x0, #0x0110, lsl #16
+ msr CPUPCR_EL3, x0
+ mov x0, #0x1
+ msr CPUPSELR_EL3, x0
+ mov x0, #0x0040
+ movk x0, #0x08D0, lsl #16
+ msr CPUPOR_EL3, x0
+ mov x0, #0x0040
+ movk x0, #0x1FF0, lsl #16
+ movk x0, #0x2, lsl #32
+ msr CPUPMR_EL3, x0
+ mov x0, #0x03fd
+ movk x0, #0x0110, lsl #16
+ msr CPUPCR_EL3, x0
+ isb
+1:
+ ret x17
+endfunc errata_a55_1221012_wa
+
+func check_errata_1221012
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1221012
+
func cortex_a55_reset_func
mov x19, x30
@@ -214,6 +261,11 @@
bl errata_a55_903758_wa
#endif
+#if ERRATA_A55_1221012
+ mov x0, x18
+ bl errata_a55_1221012_wa
+#endif
+
ret x19
endfunc cortex_a55_reset_func
@@ -253,6 +305,7 @@
report_errata ERRATA_A55_798797, cortex_a55, 798797
report_errata ERRATA_A55_846532, cortex_a55, 846532
report_errata ERRATA_A55_903758, cortex_a55, 903758
+ report_errata ERRATA_A55_1221012, cortex_a55, 1221012
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index e45d79d..599e11e 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -134,6 +134,10 @@
# only to revision <= r0p1 of the Cortex A55 cpu.
ERRATA_A55_903758 ?=0
+# Flag to apply erratum 1221012 workaround during reset. This erratum applies
+# only to revision <= r1p0 of the Cortex A55 cpu.
+ERRATA_A55_1221012 ?=0
+
# Flag to apply erratum 806969 workaround during reset. This erratum applies
# only to revision r0p0 of the Cortex A57 cpu.
ERRATA_A57_806969 ?=0
@@ -319,6 +323,10 @@
$(eval $(call assert_boolean,ERRATA_A55_903758))
$(eval $(call add_define,ERRATA_A55_903758))
+# Process ERRATA_A55_1221012 flag
+$(eval $(call assert_boolean,ERRATA_A55_1221012))
+$(eval $(call add_define,ERRATA_A55_1221012))
+
# Process ERRATA_A57_806969 flag
$(eval $(call assert_boolean,ERRATA_A57_806969))
$(eval $(call add_define,ERRATA_A57_806969))
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index a541ed3..8bfb545 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -22,6 +22,7 @@
#include <plat/common/platform.h>
#include <gpc.h>
+#include <imx_aipstz.h>
#include <imx_uart.h>
#include <plat_imx8.h>
@@ -31,6 +32,14 @@
{0},
};
+static const struct aipstz_cfg aipstz[] = {
+ {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -82,6 +91,7 @@
mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
}
+ imx_aipstz_init(aipstz);
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 9f9ba92..bd1c058 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -19,6 +19,7 @@
BL31_SOURCES += plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
+ plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \
plat/imx/imx8m/imx8mm/imx8mm_psci.c \
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index ea60466..ce55d7f 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -22,6 +22,7 @@
#include <plat/common/platform.h>
#include <gpc.h>
+#include <imx_aipstz.h>
#include <imx_uart.h>
#include <plat_imx8.h>
@@ -33,6 +34,14 @@
{0},
};
+static const struct aipstz_cfg aipstz[] = {
+ {AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -118,6 +127,8 @@
mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
}
+ imx_aipstz_init(aipstz);
+
/* config CAAM JRaMID set MID to Cortex A */
mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index 3152c72..c6bec6f 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -21,6 +21,7 @@
plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c \
plat/imx/imx8m/imx8mq/imx8mq_psci.c \
plat/imx/imx8m/gpc_common.c \
+ plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx8m_psci_common.c \
plat/imx/imx8m/imx8mq/gpc.c \
plat/imx/common/imx8_topology.c \
diff --git a/plat/imx/imx8m/imx_aipstz.c b/plat/imx/imx8m/imx_aipstz.c
new file mode 100644
index 0000000..a36e296
--- /dev/null
+++ b/plat/imx/imx8m/imx_aipstz.c
@@ -0,0 +1,24 @@
+/*
+ * copyright (c) 2019, arm limited and contributors. all rights reserved.
+ *
+ * spdx-license-identifier: bsd-3-clause
+ */
+
+#include <lib/mmio.h>
+
+#include <imx_aipstz.h>
+
+void imx_aipstz_init(const struct aipstz_cfg *aipstz_cfg)
+{
+ const struct aipstz_cfg *aipstz = aipstz_cfg;
+
+ while (aipstz->base != 0U) {
+ mmio_write_32(aipstz->base + AIPSTZ_MPR0, aipstz->mpr0);
+ mmio_write_32(aipstz->base + AIPSTZ_MPR1, aipstz->mpr1);
+
+ for (int i = 0; i < AIPSTZ_OPACR_NUM; i++)
+ mmio_write_32(aipstz->base + OPACR_OFFSET(i), aipstz->opacr[i]);
+
+ aipstz++;
+ }
+}
diff --git a/plat/imx/imx8m/include/imx_aipstz.h b/plat/imx/imx8m/include/imx_aipstz.h
new file mode 100644
index 0000000..7616862
--- /dev/null
+++ b/plat/imx/imx8m/include/imx_aipstz.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX_AIPSTZ_H
+#define IMX_AIPSTZ_H
+
+#include <lib/utils_def.h>
+
+#define AIPSTZ_MPR0 U(0x0)
+#define AIPSTZ_MPR1 U(0x4)
+
+#define AIPSTZ_OPACR_NUM U(0x5)
+#define OPACR_OFFSET(i) U((i) * 4 + 0x40)
+
+struct aipstz_cfg {
+ uintptr_t base;
+ uint32_t mpr0;
+ uint32_t mpr1;
+ uint32_t opacr[AIPSTZ_OPACR_NUM];
+};
+
+void imx_aipstz_init(const struct aipstz_cfg *aipstz_cfg);
+
+#endif /* IMX_AIPSTZ_H */
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index 1ab1af5..3afca59 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -6,6 +6,8 @@
#include <arch.h>
#include <asm_macros.S>
+#include <cortex_a72.h>
+#include <cpu_macros.S>
#include <platform_def.h>
#define K3_BOOT_REASON_COLD_RESET 0x1
@@ -89,6 +91,26 @@
ret
endfunc plat_my_core_pos
+ /* --------------------------------------------------------------------
+ * This handler does the following:
+ * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
+ * --------------------------------------------------------------------
+ */
+ .globl plat_reset_handler
+func plat_reset_handler
+ /* Only on Cortex-A72 */
+ jump_if_cpu_midr CORTEX_A72_MIDR, a72
+ ret
+
+ /* Cortex-A72 specific settings */
+a72:
+ mrs x0, CORTEX_A72_L2CTLR_EL1
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+ msr CORTEX_A72_L2CTLR_EL1, x0
+ isb
+ ret
+endfunc plat_reset_handler
+
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 29fcafd..2e5f584 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -22,6 +22,9 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+# A72 Erratum for SoC
+ERRATA_A72_859971 := 1
+
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
@@ -68,6 +71,7 @@
PLAT_BL_COMMON_SOURCES += \
lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a72.S \
${XLAT_TABLES_LIB_SRCS} \
${K3_CONSOLE_SOURCES} \