tree 5edea2e9d2624125ae4726c5e9843d0fce368b88
parent 2296df6febef9bbac508182cf4aefa5882984e39
author Govindraj Raja <govindraj.raja@arm.com> 1737504755 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1739883702 +0000

fix(cpus): workaround for Cortex-X3 erratum 3701769

Cortex-X3 erratum 3701769 that applies to r0p0, r1p0, r1p1 and r1p2
is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/

Change-Id: Ifd722e1bb8616ada2ad158297a7ca80b19a3370b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 77feb745e42296c553c33bcaea5be3304168eff3)