diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 03526a6..a8f1676 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -793,14 +793,14 @@
 
 QTI platform port
 ^^^^^^^^^^^^^^^^^
-:|M|: Saurabh Gorecha <sgorecha@codeaurora.org>
-:|G|: `sgorecha`_
 :|M|: Lachit Patel <lpatel@codeaurora.org>
 :|G|: `lachitp`_
 :|M|: Sreevyshanavi Kare <skare@codeaurora.org>
 :|G|: `sreekare`_
 :|M|: Muhammad Arsath K F <quic_mkf@quicinc.com>
 :|G|: `quic_mkf`_
+:|M|: Saurabh Gorecha <quic_sgorecha@quicinc.com>
+:|G|: `quic_sgorecha`_
 :|M|: QTI TF Maintainers <qti.trustedfirmware.maintainers@codeaurora.org>
 :|F|: docs/plat/qti.rst
 :|F|: plat/qti/
@@ -1104,6 +1104,7 @@
 .. _pangupta: https://github.com/pangupta
 .. _prabhakarlad: https://github.com/prabhakarlad
 .. _quic_mkf: https://github.com/quicmkf
+.. _quic_sgorecha: https://github.com/sgorecha
 .. _raghuncstate: https://github.com/raghuncstate
 .. _raymo200915: https://github.com/raymo200915
 .. _remi-triplefault: https://github.com/repk
@@ -1112,7 +1113,6 @@
 .. _rupsin01: https://github.com/rupsin01
 .. _rutigl: https://github.com/rutigl
 .. _sandrine-bailleux-arm: https://github.com/sandrine-bailleux-arm
-.. _sgorecha: https://github.com/sgorecha
 .. _shawnguo2: https://github.com/shawnguo2
 .. _sieumunt: https://github.com/sieumunt
 .. _smaeul: https://github.com/smaeul
diff --git a/docs/plat/mt8188.rst b/docs/plat/mt8188.rst
index 93abaa5..57b93ac 100644
--- a/docs/plat/mt8188.rst
+++ b/docs/plat/mt8188.rst
@@ -13,9 +13,9 @@
 
     Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
 
-    How to Build
-    ------------
+How to Build
+------------
 
-    .. code:: shell
+.. code:: shell
 
-           make CROSS_COMPILE=aarch64-linux-gnu- LD=aarch64-linux-gnu-gcc PLAT=mt8188 DEBUG=1 COREBOOT=1
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8188 DEBUG=1 COREBOOT=1
diff --git a/package-lock.json b/package-lock.json
index dd11559..a039bc5 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -3572,12 +3572,12 @@
       "dev": true
     },
     "node_modules/micromatch": {
-      "version": "4.0.5",
-      "resolved": "https://registry.npmjs.org/micromatch/-/micromatch-4.0.5.tgz",
-      "integrity": "sha512-DMy+ERcEW2q8Z2Po+WNXuw3c5YaUSFjAO5GsJqfEl7UjvtIuFKO6ZrKvcItdy98dwFI2N1tg3zNIdKaQT+aNdA==",
+      "version": "4.0.8",
+      "resolved": "https://registry.npmjs.org/micromatch/-/micromatch-4.0.8.tgz",
+      "integrity": "sha512-PXwfBhYu0hBCPw8Dn0E+WDYb7af3dSLVWKi3HGv84IdF4TyFoC0ysxFd0Goxw7nSv4T/PzEJQxsYsEiFCKo2BA==",
       "dev": true,
       "dependencies": {
-        "braces": "^3.0.2",
+        "braces": "^3.0.3",
         "picomatch": "^2.3.1"
       },
       "engines": {
@@ -4903,7 +4903,7 @@
       }
     },
     "tools/conventional-changelog-tf-a": {
-      "version": "2.11.0",
+      "version": "2.12.0",
       "dev": true,
       "license": "BSD-3-Clause",
       "dependencies": {
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 82f9fd3..dfa409f 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -48,6 +48,7 @@
 #define MBOX_CMD_GET_IDCODE				0x10
 #define MBOX_CMD_GET_USERCODE				0x13
 #define MBOX_CMD_GET_CHIPID				0x12
+#define MBOX_CMD_FPGA_CONFIG_COMP			0x45
 #define MBOX_CMD_REBOOT_HPS				0x47
 
 /* Reconfiguration Commands */
@@ -260,4 +261,6 @@
 int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
 int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
 
+int mailbox_send_fpga_config_comp(void);
+
 #endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 5d31e99..94895ba 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -622,6 +622,22 @@
 	return MBOX_RET_OK;
 }
 
+int mailbox_send_fpga_config_comp(void)
+{
+	int ret;
+
+	ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_FPGA_CONFIG_COMP, NULL, 0U,
+				 CMD_CASUAL, NULL, NULL);
+
+	if (ret != 0) {
+		INFO("SOCFPGA: FPGA configuration complete response, Return Code: 0x%x\n",
+			MBOX_RESP_ERR(-ret));
+		return MBOX_RET_ERROR;
+	}
+
+	return MBOX_RET_OK;
+}
+
 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
 {
 	int status;
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index c7d7076..f653318 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -404,10 +404,11 @@
 	uint32_t brg_lst = 0;
 #endif
 
+/**************** SOC2FPGA ****************/
+
 	/* Enable s2f bridge */
 	socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
-/**************** SOC2FPGA ****************/
 	brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
 	if ((brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA)
 		&& ((brg_lst & RSTMGR_BRGMODRSTMASK_SOC2FPGA) != 0)) {
@@ -593,6 +594,8 @@
 	}
 #endif
 
+/**************** FPGA2SOC ****************/
+
 	/* Enable f2s bridge */
 	socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
 				&f2s_force_drain, &f2s_en,
@@ -603,89 +606,28 @@
 	if ((brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC)
 		&& ((brg_lst & RSTMGR_BRGMODRSTMASK_FPGA2SOC) != 0)) {
 		/*
-		 * To request handshake
-		 * Write Reset Manager hdsken[fpgahsen] = 1
+		 * To deassert reset
+		 * Write Reset Manager brgmodrst[fpga2soc] = 0
 		 */
-		VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
-		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
+		VERBOSE("Deassert F2S ...\n");
+		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+				RSTMGR_BRGMODRST_FPGA2SOC);
 
 		/*
-		 * To request handshake
-		 * Write Reset Manager hdskreq[fpgahsreq] = 1
+		 * To clear handshake fpgahsack
+		 * Write Reset Manager hdskreq[fpgahsack] = 1
 		 */
-		VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
-		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
-
-		/*
-		 * To poll idle status
-		 * Read Reset Manager hdskack[fpgahsack] = 1
-		 */
-		VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
-		if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
-				& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
-			ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-				RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
-				300);
-		}
-
-		if (ret < 0) {
-			ERROR("FPGA bridge fpga handshake fpgahsreq: Timeout\n");
-		}
-
-		/*
-		 * To fence and drain traffic
-		 * Write Reset Manager hdskreq[f2s_flush_req] = 1
-		 */
-		VERBOSE("Set F2S hdskreq(f2s_flush_req) ...\n");
-		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
-			RSTMGR_HDSKREQ_FPGA2SOCREQ);
-
-		/*
-		 * To poll idle status
-		 * Read Reset Manager hdskack[f2s_flush_ack] = 1
-		 */
-		VERBOSE("Get F2S hdskack(f2s_flush_ack) ...\n");
-		if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
-				& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
-			ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-				RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK,
-				300);
-		}
-
-		if (ret < 0) {
-			ERROR("F2S bridge fpga handshake f2sdram_flush_req: Timeout\n");
-		}
+		VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
+				RSTMGR_HDSKACK_FPGAHSACK);
 
 		/*
 		 * To clear idle request
-		 * Write Reset Manager hdskreq[fpgahsreq] = 1
+		 * Write Reset Manager hdskreq[fpgahsreq] = 0
 		 */
 		VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
-		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
-
-		/*
-		 * To clear idle request
-		 * Write Reset Manager hdskreq[f2s_flush_req] = 1
-		 */
-		VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
 		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
-			RSTMGR_HDSKREQ_FPGA2SOCREQ);
-
-		/*
-		 * To poll idle status
-		 * Read Reset Manager hdskack[f2s_flush_ack] = 0
-		 */
-		VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
-		if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
-				& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
-			ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-				RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
-				300);
-		}
-
-		if (ret < 0) {
-			ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
-		}
+				RSTMGR_HDSKACK_FPGAHSREQ);
 
 		/*
 		 * To poll idle status
@@ -695,8 +637,9 @@
 		if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
 				& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
 			ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-				RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
-				300);
+						RSTMGR_HDSKACK_FPGAHSACK,
+						RSTMGR_HDSKACK_FPGAHSACK_DASRT,
+						1000);
 				}
 
 		if (ret < 0) {
@@ -704,27 +647,46 @@
 		}
 
 		/*
-		 * To assert reset
-		 * Write Reset Manager brgmodrst[fpga2soc] = 1
+		 * To clear handshake f2s_flush_ack
+		 * Write Reset Manager hdskreq[f2s_flush_ack] = 1
 		 */
-		VERBOSE("Assert F2S ...\n");
-		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
-
-		udelay(1000);
+		VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
+				RSTMGR_HDSKACK_F2S_FLUSH);
 
 		/*
-		 * To deassert reset
-		 * Write Reset Manager brgmodrst[fpga2soc] = 0
+		 * To clear idle request
+		 * Write Reset Manager hdskreq[f2s_flush_req] = 0
 		 */
-		VERBOSE("Deassert F2S ...\n");
-		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
+		VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
+		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+				RSTMGR_HDSKREQ_F2S_FLUSH);
 
-		/* Write System Manager f2s bridge control register[f2soc_enable] = 1 */
+		/*
+		 * To poll idle status
+		 * Read Reset Manager hdskack[f2s_flush_ack] = 0
+		 */
+		VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
+		if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
+				& RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
+			ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
+						RSTMGR_HDSKACK_FPGA2SOCACK,
+						RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
+						1000);
+		}
+
+		if (ret < 0) {
+			ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
+		}
+
+		/* Write System Manager f2s_bridge_ctrl [f2soc_enable] = 1 */
 		VERBOSE("Deassert F2S f2soc_enable ...\n");
 		mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
-			SYSMGR_F2S_BRIDGE_CTRL_EN);
+				SYSMGR_F2S_BRIDGE_CTRL_EN);
 	}
 
+/**************** FPGA2SDRAM ****************/
+
 	/* Enable FPGA2SDRAM bridge */
 	if ((brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0)
 		&& ((brg_lst & RSTMGR_BRGMODRSTMASK_F2SDRAM0) != 0)) {
@@ -932,6 +894,8 @@
 	uint32_t f2s_respempty = 0;
 	uint32_t f2s_cmdidle = 0;
 
+/**************** SOC2FPGA ****************/
+
 	/* Disable s2f bridge */
 	socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
@@ -973,6 +937,8 @@
 		udelay(1000);
 	}
 
+/**************** LWSOCFPGA ****************/
+
 	/* Disable LWSOC2FPGA bridge */
 	if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
 		/*
@@ -1035,6 +1001,8 @@
 	}
 #endif
 
+/**************** FPGA2SOC ****************/
+
 	/* Disable f2s bridge */
 	socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
 				&f2s_force_drain, &f2s_en,
@@ -1044,67 +1012,90 @@
 	if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
 		/*
 		 * To request handshake
+		 * Write Reset Manager hdsken[f2soc_flush] = 1
+		 */
+		VERBOSE("Enable FPGA hdsken(f2soc_flush) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
+				RSTMGR_HDSKEN_F2S_FLUSH);
+
+		/*
+		 * To request handshake
 		 * Write Reset Manager hdsken[fpgahsen] = 1
 		 */
-		VERBOSE("Set FPGA hdsken(fpgahsen) ...\n");
+		VERBOSE("Enable FPGA hdsken(fpgahsen) ...\n");
 		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
 
 		/*
-		 * To clear handshake request
-		 * Write Reset Manager hdskreq[fpgahsreq] = 0
+		 * To clear handshake fpgahsack
+		 * Write Reset Manager hdskack[fpgahsack] = 1
 		 */
-		VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
-		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
+		VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
+				RSTMGR_HDSKACK_FPGAHSACK);
 
 		/*
-		 * To clear handshake request
-		 * Write Reset Manager hdskreq[f2s_flush_req] = 0
+		 * To set handshake request
+		 * Write Reset Manager hdskreq[fpgahsreq] = 1
 		 */
-		VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
-		mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
-			RSTMGR_HDSKREQ_FPGA2SOCREQ);
+		VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+				RSTMGR_HDSKREQ_FPGAHSREQ);
 
 		/*
 		 * To poll idle status
-		 * Read Reset Manager hdskack[f2s_flush_ack] = 0
-		 */
-		VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
-		ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-			RSTMGR_HDSKACK_FPGA2SOCACK, RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
-			300);
-
-		if (ret < 0) {
-			ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
-		}
-
-		/*
-		 * To poll idle status
-		 * Read Reset Manager hdskack[fpgahsack] = 0
+		 * Read Reset Manager hdskack[fpgahsack] = 1
 		 */
 		VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
 		ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
-			RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
-			300);
+					RSTMGR_HDSKACK_FPGAHSACK,
+					RSTMGR_HDSKACK_FPGAHSACK,
+					1000);
 
 		if (ret < 0) {
 			ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
 		}
 
 		/*
+		 * To clear handshake f2s_flush_ack
+		 * Write Reset Manager hdskack[f2s_flush_ack] = 1
+		 */
+		VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
+				RSTMGR_HDSKACK_F2S_FLUSH);
+
+		/*
+		 * To set handshake request
+		 * Write Reset Manager hdskreq[f2s_flush_req] = 1
+		 */
+		VERBOSE("Set FPGA hdskreq(f2s_flush_req) ...\n");
+		mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
+				RSTMGR_HDSKREQ_F2S_FLUSH);
+
+		/*
+		 * To poll idle status
+		 * Read Reset Manager hdskack[f2s_flush_ack] = 1
+		 */
+		VERBOSE("Get FPGA hdskack(f2s_flush_ack) ...\n");
+		ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
+					RSTMGR_HDSKACK_FPGA2SOCACK,
+					RSTMGR_HDSKACK_F2S_FLUSH,
+					1000);
+
+		if (ret < 0) {
+			ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
+		}
+
+		/*
 		 * To assert reset
 		 * Write Reset Manager brgmodrst[fpga2soc] = 1
 		 */
 		VERBOSE("Assert F2S ...\n");
-		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), RSTMGR_BRGMODRST_FPGA2SOC);
-
-		udelay(1000);
-
-		/* Write System Manager f2s bridge control register[f2soc_enable] = 0 */
-		VERBOSE("Assert F2S f2soc_enable ...\n");
-		mmio_clrbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
-			SYSMGR_F2S_BRIDGE_CTRL_EN);
+		mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
+				RSTMGR_BRGMODRST_FPGA2SOC);
 	}
 
+/**************** FPGA2SDRAM ****************/
+
 	/* Disable FPGA2SDRAM bridge */
 	if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
 		/*
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 3c223c1..68deab9 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -222,6 +222,19 @@
 	unsigned int size = 0;
 	unsigned int resp_len = ARRAY_SIZE(response);
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	/*
+	 * To trigger isolation
+	 * FPGA configuration complete signal should be de-asserted
+	 */
+	INFO("SOCFPGA: Request SDM to trigger isolation\n");
+	status = mailbox_send_fpga_config_comp();
+
+	if (status < 0) {
+		INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n");
+	}
+#endif
+
 	request_type = RECONFIGURATION;
 
 	if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) {
diff --git a/poetry.lock b/poetry.lock
index 9a90704..91203d2 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.8.2 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.8.3 and should not be changed by hand.
 
 [[package]]
 name = "alabaster"
@@ -869,23 +869,23 @@
 
 [[package]]
 name = "setuptools"
-version = "74.1.2"
+version = "75.3.0"
 description = "Easily download, build, install, upgrade, and uninstall Python packages"
 optional = false
 python-versions = ">=3.8"
 files = [
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 ]
 
 [package.extras]
 check = ["pytest-checkdocs (>=2.4)", "pytest-ruff (>=0.2.1)", "ruff (>=0.5.2)"]
-core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.text (>=3.7)", "more-itertools (>=8.8)", "packaging (>=24)", "platformdirs (>=2.6.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
+core = ["importlib-metadata (>=6)", "importlib-resources (>=5.10.2)", "jaraco.collections", "jaraco.functools", "jaraco.text (>=3.7)", "more-itertools", "more-itertools (>=8.8)", "packaging", "packaging (>=24)", "platformdirs (>=4.2.2)", "tomli (>=2.0.1)", "wheel (>=0.43.0)"]
 cover = ["pytest-cov"]
 doc = ["furo", "jaraco.packaging (>=9.3)", "jaraco.tidelift (>=1.4)", "pygments-github-lexers (==0.0.5)", "pyproject-hooks (!=1.1)", "rst.linker (>=1.9)", "sphinx (>=3.5)", "sphinx-favicon", "sphinx-inline-tabs", "sphinx-lint", "sphinx-notfound-page (>=1,<2)", "sphinx-reredirects", "sphinxcontrib-towncrier", "towncrier (<24.7)"]
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 [[package]]
 name = "shellingham"