feat(dsu): save/restore DSU PMU register
Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved
Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 73b2d76..d32ead4 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -795,7 +795,21 @@
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
-#define CLUSTERPWRDN p15, 0, c15, c3, 6
+#define CLUSTERPWRDN p15, 0, c15, c3, 6
+#define CLUSTERPMCR p15, 0, c15, c5, 0
+#define CLUSTERPMCNTENSET p15, 0, c15, c5, 1
+#define CLUSTERPMCCNTR p15, 0, c15, c6, 0
+#define CLUSTERPMOVSSET p15, 0, c15, c5, 3
+#define CLUSTERPMOVSCLR p15, 0, c15, c5, 4
+#define CLUSTERPMSELR p15, 0, c15, c5, 5
+#define CLUSTERPMXEVTYPER p15, 0, c15, c6, 1
+#define CLUSTERPMXEVCNTR p15, 0, c15, c6, 2
+
+/* CLUSTERPMCR register definitions */
+#define CLUSTERPMCR_E_BIT BIT(0)
+#define CLUSTERPMCR_N_SHIFT U(11)
+#define CLUSTERPMCR_N_MASK U(0x1f)
+
/* CLUSTERPWRDN register definitions */
#define DSU_CLUSTER_PWR_OFF 0