plat/arm: Fix BL31_BASE when RESET_TO_BL31=1

The value of BL31_BASE currently depends on the size of BL31. This
causes problems in the RESET_TO_BL31 case because the value of
BL31_BASE is used in the model launch parameters, which often changes.

Therefore, this patch fixes BL31_BASE to the middle of Trusted SRAM,
to avoid further model parameter changes in future.

Change-Id: I6d7fa4fe293717d84768974679539c0e0cb6d935
Signed-off-by: David Cunado <david.cunado@arm.com>
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index f66bde3..1ff080d 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1593,15 +1593,15 @@
     -C cluster0.NUM_CORES=4                                      \
     -C cluster1.NUM_CORES=4                                      \
     -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBAR=0x04023000                            \
-    -C cluster0.cpu1.RVBAR=0x04023000                            \
-    -C cluster0.cpu2.RVBAR=0x04023000                            \
-    -C cluster0.cpu3.RVBAR=0x04023000                            \
-    -C cluster1.cpu0.RVBAR=0x04023000                            \
-    -C cluster1.cpu1.RVBAR=0x04023000                            \
-    -C cluster1.cpu2.RVBAR=0x04023000                            \
-    -C cluster1.cpu3.RVBAR=0x04023000                            \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000    \
+    -C cluster0.cpu0.RVBAR=0x04020000                            \
+    -C cluster0.cpu1.RVBAR=0x04020000                            \
+    -C cluster0.cpu2.RVBAR=0x04020000                            \
+    -C cluster0.cpu3.RVBAR=0x04020000                            \
+    -C cluster1.cpu0.RVBAR=0x04020000                            \
+    -C cluster1.cpu1.RVBAR=0x04020000                            \
+    -C cluster1.cpu2.RVBAR=0x04020000                            \
+    -C cluster1.cpu3.RVBAR=0x04020000                            \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000    \
     --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000    \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
@@ -1678,15 +1678,15 @@
     -C bp.secure_memory=1                                        \
     -C bp.tzc_400.diagnostics=1                                  \
     -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBARADDR=0x04023000                        \
-    -C cluster0.cpu1.RVBARADDR=0x04023000                        \
-    -C cluster0.cpu2.RVBARADDR=0x04023000                        \
-    -C cluster0.cpu3.RVBARADDR=0x04023000                        \
-    -C cluster1.cpu0.RVBARADDR=0x04023000                        \
-    -C cluster1.cpu1.RVBARADDR=0x04023000                        \
-    -C cluster1.cpu2.RVBARADDR=0x04023000                        \
-    -C cluster1.cpu3.RVBARADDR=0x04023000                        \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000    \
+    -C cluster0.cpu0.RVBARADDR=0x04020000                        \
+    -C cluster0.cpu1.RVBARADDR=0x04020000                        \
+    -C cluster0.cpu2.RVBARADDR=0x04020000                        \
+    -C cluster0.cpu3.RVBARADDR=0x04020000                        \
+    -C cluster1.cpu0.RVBARADDR=0x04020000                        \
+    -C cluster1.cpu1.RVBARADDR=0x04020000                        \
+    -C cluster1.cpu2.RVBARADDR=0x04020000                        \
+    -C cluster1.cpu3.RVBARADDR=0x04020000                        \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000    \
     --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000    \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \