fix(cpus): workaround for Neoverse-N3 erratum 3699563
Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-3050973/latest/
Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 3944fc0..fd7a387 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -22,6 +22,7 @@
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
#include <neoverse_n2.h>
+#include <neoverse_n3.h>
#if ERRATA_A520_2938996 || ERRATA_X4_2726228
unsigned int check_if_affected_core(void)
@@ -123,6 +124,12 @@
break;
#endif /* ERRATA_N2_3701773 */
+#if ERRATA_N3_3699563
+ case EXTRACT_PARTNUM(NEOVERSE_N3_MIDR):
+ if (check_erratum_neoverse_n3_3699563(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_N3_3699563 */
default:
break;
}