Support for NXP's i.MX8 SoCs IPC

NXP's i.MX8 SoCs have system controller (M4 core)
which takes control of clock management, power management,
partition management, PAD management etc., other
clusters like Cortex-A35 can send out command via MU
(Message Unit) to system controller for clock/power
management etc..

This patch adds basic IPC(inter-processor communication) support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
diff --git a/plat/imx/common/include/imx8_iomux.h b/plat/imx/common/include/imx8_iomux.h
new file mode 100644
index 0000000..7a7f549
--- /dev/null
+++ b/plat/imx/common/include/imx8_iomux.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX8_IOMUX_H__
+#define __IMX8_IOMUX_H__
+
+#define PADRING_IFMUX_EN_SHIFT		31
+#define PADRING_IFMUX_EN_MASK		(1 << PADRING_IFMUX_EN_SHIFT)
+#define PADRING_GP_EN_SHIFT		30
+#define PADRING_GP_EN_MASK		(1 << PADRING_GP_EN_SHIFT)
+#define PADRING_IFMUX_SHIFT		27
+#define PADRING_IFMUX_MASK		(0x7 << PADRING_IFMUX_SHIFT)
+#define PADRING_CONFIG_SHIFT		25
+#define PADRING_CONFIG_MASK		(0x3 << PADRING_CONFIG_SHIFT)
+#define PADRING_LPCONFIG_SHIFT		23
+#define PADRING_LPCONFIG_MASK		(0x3 << PADRING_LPCONFIG_SHIFT)
+#define PADRING_PULL_SHIFT		5
+#define PADRING_PULL_MASK		(0x3 << PADRING_PULL_SHIFT)
+#define PADRING_DSE_SHIFT		0
+#define PADRING_DSE_MASK		(0x7 << PADRING_DSE_SHIFT)
+
+#endif	/* __IMX8_IOMUX_H__ */