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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / 5819e23bc47c860872141caf42bddddb1b8679a5 / . / include / lib / cpus / aarch64 / neoverse_n2.h
blob: 8ba62a3f75430b740a6fa10e62b790910bcd8dc7 [file] [log] [blame]
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]1/*
Bipin Ravi4618b2b2021-03-31 10:10:27 -0500[diff] [blame]2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_N2_H
8#define NEOVERSE_N2_H
9
10/* Neoverse N2 ID register for revision r0p0 */
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]11#define NEOVERSE_N2_MIDR U(0x410FD490)
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]12
13/*******************************************************************************
14 * CPU Power control register
15 ******************************************************************************/
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]16#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
17#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]18
19/*******************************************************************************
20 * CPU Extended Control register specific definitions.
21 ******************************************************************************/
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]22#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
23#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
24#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]25
26/*******************************************************************************
27 * CPU Auxiliary Control register specific definitions.
28 ******************************************************************************/
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]29#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
30#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
nayanpatel-arm5819e232021-10-06 15:31:24 -0700[diff] [blame^]31#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
Bipin Ravi65e04f22021-03-30 16:08:32 -0500[diff] [blame]32
33/*******************************************************************************
34 * CPU Auxiliary Control register 2 specific definitions.
35 ******************************************************************************/
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]36#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
37#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]38
Bipin Ravi7cfae932021-08-30 13:02:51 -0500[diff] [blame]39/*******************************************************************************
40 * CPU Auxiliary Control register 5 specific definitions.
41 ******************************************************************************/
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700[diff] [blame]42#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
43#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
44
45/*******************************************************************************
46 * CPU Auxiliary Control register specific definitions.
47 ******************************************************************************/
48#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
49#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
50#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
51#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
Bipin Ravi7cfae932021-08-30 13:02:51 -0500[diff] [blame]52
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100[diff] [blame]53#endif /* NEOVERSE_N2_H */