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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / 901b0a3015a652d9eb66c063b0984fade9adf08f / . / include / lib / cpus / aarch64 / dsu_def.h
blob: 577de619959f6b972cd78fa190b2cf812846c0af [file] [log] [blame]
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]1/*
Bipin Ravi7e3273e2021-12-22 14:35:21 -0600[diff] [blame]2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef DSU_DEF_H
8#define DSU_DEF_H
9
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]11
12/********************************************************************
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]13 * DSU Cluster Configuration registers definitions
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]14 ********************************************************************/
15#define CLUSTERCFR_EL1 S3_0_C15_C3_0
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]16
17#define CLUSTERCFR_ACP_SHIFT U(11)
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]18
19/********************************************************************
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]20 * DSU Cluster Main Revision ID registers definitions
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]21 ********************************************************************/
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]22#define CLUSTERIDR_EL1 S3_0_C15_C3_1
23
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]24#define CLUSTERIDR_REV_SHIFT U(0)
25#define CLUSTERIDR_REV_BITS U(4)
26#define CLUSTERIDR_VAR_SHIFT U(4)
27#define CLUSTERIDR_VAR_BITS U(4)
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]28
29/********************************************************************
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]30 * DSU Cluster Auxiliary Control registers definitions
31 ********************************************************************/
32#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
33
Louis Mayencourt0e985d72019-04-09 16:29:01 +0100[diff] [blame]34#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
Bipin Ravi7e3273e2021-12-22 14:35:21 -0600[diff] [blame]35#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
Louis Mayencourt0e985d72019-04-09 16:29:01 +0100[diff] [blame]36
Louis Mayencourt2c3b76c2019-04-09 14:11:06 +0100[diff] [blame]37/********************************************************************
38 * Masks applied for DSU errata workarounds
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]39 ********************************************************************/
Antonio Nino Diaz1a74e4a2019-02-11 13:34:15 +0000[diff] [blame]40#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
John Tsichritzis8a677182018-07-23 09:11:59 +0100[diff] [blame]41
42#endif /* DSU_DEF_H */