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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / 47ea303389f6d0ac81617366973ece9d93dc49c9 / lib / cpus / aarch64 / cpu_helpers.S
  1. 3f721c6 fix(cpus): assert invalid cpu_ops obtained by Thaddeus Serna · 2 years, 1 month ago
  2. dd9fae1 refactor(cpus): convert print_errata_status to C by Boyan Karatotev · 2 years, 6 months ago
  3. 6bb96fa refactor(cpus): rename errata_report.h to errata.h by Boyan Karatotev · 2 years, 6 months ago
  4. 007433d refactor(cpus): move cpu_ops field defines to a header by Boyan Karatotev · 2 years, 6 months ago
  5. a59cddf Merge changes from topic "bk/errata_refactor" into integration by Manish Pandey · 2 years, 5 months ago
  6. 7c25a3a chore(cpus): remove redundant asserts by Boyan Karatotev · 2 years, 6 months ago
  7. 42d4d3b refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years, 9 months ago
  8. 9b2510b fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 by Bipin Ravi · 3 years, 5 months ago
  9. 2e61d68 fix: random typos in tf-a code base by Olivier Deprez · 4 years, 2 months ago
  10. 1994e56 arm_fpga: Add support for unknown MPIDs by Javier Almansa Sobrino · 5 years ago
  11. 601e3ed lib: cpus: sanity check pointers before use by Varun Wadekar · 6 years ago
  12. 8094262 Neoverse N1 Errata Workaround 1542419 by laurenw-arm · 6 years ago
  13. c2ad38c Tegra: Support for scatterfile for the BL31 image by Varun Wadekar · 7 years ago
  14. 09d40e0 Sanitise includes across codebase by Antonio Nino Diaz · 7 years ago
  15. fe007b2 Add support for dynamic mitigation for CVE-2018-3639 by Dimitris Papastamos · 7 years ago
  16. 2c3a107 Rename symbols and files relating to CVE-2017-5715 by Dimitris Papastamos · 7 years ago
  17. 9ec3921 Check presence of fix for errata 843419 in Cortex-A53 by Jonathan Wright · 7 years ago
  18. a205a56 Fixup `SMCCC_ARCH_FEATURES` semantics by Dimitris Papastamos · 7 years ago
  19. b1d27b4 bl2-el3: Add BL2_EL3 image by Roberto Vargas · 8 years ago
  20. 22fa58c Use a callee-saved register to be AAPCS-compliant by dp-arm · 8 years ago
  21. 82cb2c1 Use SPDX license identifiers by dp-arm · 8 years ago
  22. 044bb2f Remove build option `ASM_ASSERTION` by Antonio Nino Diaz · 8 years ago
  23. b75dc0e Add workaround for ARM Cortex-A53 erratum 855873 by Andre Przywara · 9 years ago
  24. 10bcd76 Report errata workaround status to console by Jeenu Viswambharan · 9 years ago
  25. 3d8256b Use #ifdef for IMAGE_BL* instead of #if by Masahiro Yamada · 9 years ago
  26. 55c70cb Correct system include order by David Cunado · 9 years ago
  27. 5dd9dbb Add provision to extend CPU operations at more levels by Jeenu Viswambharan · 9 years ago
  28. 1319e7b Make cpu operations warning a VERBOSE print by Soby Mathew · 9 years ago
  29. 54035fc Disable non-temporal hint on Cortex-A53/57 by Sandrine Bailleux · 10 years ago
  30. 8b77962 Add support to indicate size and end of assembly functions by Kévin Petit · 10 years ago
  31. 12e7c4a Initialise cpu ops after enabling data cache by Vikram Kanigiri · 11 years ago
  32. 683f788 Fix the Cortex-A57 reset handler register usage by Soby Mathew · 11 years ago
  33. 79a97b2 Call reset handlers upon BL3-1 entry. by Yatharth Kochar · 11 years ago
  34. 0999734 Invalidate the dcache after initializing cpu-ops by Soby Mathew · 11 years ago
  35. 7395a72 Apply errata workarounds only when major/minor revisions match. by Soby Mathew · 11 years ago
  36. d3f70af Add CPU specific crash reporting handlers by Soby Mathew · 11 years ago
  37. add4035 Add CPU specific power management operations by Soby Mathew · 11 years ago
  38. 24fb838 Add platform API for reset handling by Soby Mathew · 11 years ago
  39. 9b47684 Introduce framework for CPU specific operations by Soby Mathew · 11 years ago