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review.trustedfirmware.org / sandbox / arthur / trustedfirmware-a / 6fc9c1cdb96349d16bf4f2d76e4e8ad6c2548f99 / plat / intel / soc / n5x / include
  1. 5f06bff fix(intel): fix Agilex and N5X clock manager to main PLL C0 by Jit Loon Lim · 2 years, 8 months ago
  2. 02a9d70 feat(intel): implement timer init divider via CPU frequency for N5X by Sieu Mun Tang · 3 years, 1 month ago
  3. f0f631f Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 3 years, 3 months ago
  4. f65bdf3 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 3 years, 4 months ago
  5. 11f4f03 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 3 years, 3 months ago
  6. f571183 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 3 years, 5 months ago
  7. 325eb35 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 3 years, 5 months ago