- b57e16a refactor(amu): use new AMU feature check routines by Andre Przywara · 2 years, 5 months ago
- 603a0c6 refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED by Andre Przywara · 2 years, 9 months ago
- 6437a09 refactor(spe): enable FEAT_SPE for FEAT_STATE_CHECKED by Andre Przywara · 2 years, 9 months ago
- a4c6958 Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration by Manish Pandey · 2 years, 5 months ago
- 42d4d3b refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 by Arvind Ram Prakash · 2 years, 9 months ago
- 9a90d72 style: remove useless trailing semicolon and line continuations by Elyes Haouas · 2 years, 6 months ago
- fc8d2d3 refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED by Andre Przywara · 2 years, 9 months ago
- fd1dd4c refactor(cpufeat): wrap CPU ID register field isolation by Andre Przywara · 2 years, 6 months ago
- bb22891 feat(debug): add AARCH32 CP15 fault registers by Yann Gautier · 6 years ago
- dcb31ff feat(gic): add APIs to raise NS and S-EL1 SGIs by Florian Lugou · 4 years ago
- 96a8ed1 feat(bl2): add support to separate no-loadable sections by Jiafei Pan · 3 years, 5 months ago
- d0ec1cc feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX by johpow01 · 3 years, 8 months ago
- 81e2ff1 refactor(amu): detect architected counters at runtime by Chris Kay · 4 years, 2 months ago
- 33b9be6 refactor(amu): factor out register accesses by Chris Kay · 4 years, 2 months ago
- 596d20d fix(pie): invalidate data cache in the entire image range if PIE is enabled by Zelalem Aweke · 3 years, 10 months ago
- 8fcd3d9 feat(trf): enable trace filter control register access from lower NS EL by Manish V Badarkhe · 4 years, 1 month ago
- 5de20ec feat(trf): initialize trap settings of trace filter control registers access by Manish V Badarkhe · 4 years, 1 month ago
- d4582d3 feat(sys_reg_trace): enable trace system registers access from lower NS ELs by Manish V Badarkhe · 4 years, 1 month ago
- 2031d61 feat(sys_reg_trace): initialize trap settings of trace system registers access by Manish V Badarkhe · 4 years, 1 month ago
- 4324a14 Add PIE support for AARCH32 by Yann Gautier · 4 years, 10 months ago
- fb4f511 Avoid the use of linker *_SIZE__ macros by Yann Gautier · 5 years ago
- 4e04478 arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms by Chris Kay · 4 years, 5 months ago
- 873d424 Enable v8.6 AMU enhancements (FEAT_AMUv1p1) by johpow01 · 4 years, 10 months ago
- 0063dd1 Add support for FEAT_MTPMU for Armv8.6 by Javier Almansa Sobrino · 4 years, 9 months ago
- 2be491b aarch64/arm: Add compiler barrier to barrier instructions by Andre Przywara · 4 years, 10 months ago
- d7b5f40 Increase type widths to satisfy width requirements by Jimmy Brisson · 5 years ago
- f3ccf03 TF-A AMU extension: fix detection of group 1 counters. by Alexei Fedorov · 5 years ago
- 9cf7f35 Provide a hint to power controller for DSU cluster power down by Madhukar Pappireddy · 6 years ago
- 1150416 locks: bakery: use is_dcache_enabled() helper by Masahiro Yamada · 5 years ago
- 3443a70 Fix MISRA C issues in BL1/BL2/BL31 by John Powell · 5 years ago
- 6cdd55d Merge "el3_entrypoint_common: avoid overwriting arg3" into integration by Manish Pandey · 5 years ago
- ccfb5c8 Use Speculation Barrier instruction for v8.5 cores by Madhukar Pappireddy · 5 years ago
- 6bc2438 aarch32: stop speculative execution past exception returns by Madhukar Pappireddy · 5 years ago
- 30f3100 el3_entrypoint_common: avoid overwriting arg3 by Yann Gautier · 6 years ago
- e34cc0c Changes to support updated register usage in SMCCC v1.2 by Madhukar Pappireddy · 6 years ago
- 0a12302 Add missing support for BL2_AT_EL3 in XIP memory by Lionel Debieve · 6 years ago
- c3e8b0b AArch32: Disable Secure Cycle Counter by Alexei Fedorov · 6 years ago
- d5dfdeb Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ by Julius Werner · 6 years ago
- c250cc3 SSBS: init SPSR register with default SSBS value by John Tsichritzis · 6 years ago
- 52e9108 console: update skeleton by Ambroise Vincent · 6 years ago
- e1abd56 arch: add some defines for generic timer registers by Yann Gautier · 6 years ago
- fbd8f6c aarch32: Allow compiling with soft-float toolchain by Manish Pandey · 6 years ago
- be3991c Console: remove deprecated finish_console_register by Ambroise Vincent · 6 years ago
- bd39370 Cortex-A53: Workarounds for 819472, 824069 and 827319 by Ambroise Vincent · 6 years ago
- c8b96e4 Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd by Antonio Niño Díaz · 6 years ago
- 8f73663 plat/arm: Support for Cortex A5 in FVP Versatile Express platform by Usama Arif · 7 years ago
- a5aa25a Division functionality for cores that dont have divide hardware. by Usama Arif · 7 years ago
- ed4fc6f Disable processor Cycle Counting in Secure state by Antonio Nino Diaz · 6 years ago
- 29a2413 drivers: generic_delay_timer: Assert presence of Generic Timer by Antonio Nino Diaz · 6 years ago
- 2559b2c xlat v2: Dynamically detect need for CnP bit by Antonio Nino Diaz · 7 years ago
- 09d40e0 Sanitise includes across codebase by Antonio Nino Diaz · 7 years ago
- f5478de Reorganize architecture-dependent header files by Antonio Nino Diaz · 7 years ago