| commit | 0e0521bdfce73be7dbded23e560b3dab1ff1af2d | [log] [tgz] |
|---|---|---|
| author | johpow01 <john.powell@arm.com> | Tue Jun 02 13:14:11 2020 -0500 |
| committer | John Powell <john.powell@arm.com> | Thu Jun 25 19:58:35 2020 +0000 |
| tree | cd1fba5d1538fae0b9d808bd9244d7d9e661fc44 | |
| parent | 24cdbb22a9da2eb7d07592774777012552a5dd41 [diff] |
Workaround for Neoverse N1 erratum 1800710 Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 6b6c639..78a80f6 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst
@@ -278,6 +278,9 @@ - ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. +- ``ERRATA_N1_1800710``: This applies errata 1800710 workaround to Neoverse-N1 + CPU. This needs to be enabled only for revisions <= r4p0 of the CPU. + DSU Errata Workarounds ----------------------