diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst
index 9f62b7c..ab39723 100644
--- a/docs/components/romlib-design.rst
+++ b/docs/components/romlib-design.rst
@@ -106,7 +106,7 @@
 In the below example the usage of ROMLIB together with mbed TLS is demonstrated
 to showcase the benefits of library at ROM - it's not mandatory.
 
-::
+.. code:: shell
 
     make PLAT=fvp                                                   \
     MBEDTLS_DIR=</path/to/mbedtls/>                                 \
diff --git a/docs/components/sdei.rst b/docs/components/sdei.rst
index 8c08789..7b6cc91 100644
--- a/docs/components/sdei.rst
+++ b/docs/components/sdei.rst
@@ -224,7 +224,7 @@
 The SDEI dispatcher implementation provides ``sdei_dispatch_event()`` API for
 this purpose. The API has the following signature:
 
-::
+.. code:: c
 
         int sdei_dispatch_event(int ev_num);
 
diff --git a/docs/components/secure-partition-manager-design.rst b/docs/components/secure-partition-manager-design.rst
index 31276cd..88052c5 100644
--- a/docs/components/secure-partition-manager-design.rst
+++ b/docs/components/secure-partition-manager-design.rst
@@ -130,7 +130,7 @@
 Then build TF-A with SPM support and include the Standalone MM Secure Partition
 image in the FIP:
 
-::
+.. code:: shell
 
     BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \
     make PLAT=fvp ENABLE_SPM=1 ARM_BL31_IN_DRAM=1 fip all
diff --git a/docs/design/auth-framework.rst b/docs/design/auth-framework.rst
index 49f0def..7a742d5 100644
--- a/docs/design/auth-framework.rst
+++ b/docs/design/auth-framework.rst
@@ -408,7 +408,7 @@
 
 An IPL for each type must be registered using the following macro:
 
-::
+.. code:: c
 
     REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param)
 
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 27d0948..e9384e6 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2304,7 +2304,7 @@
 Subscribed handlers must be of type ``pubsub_cb_t``, with following function
 signature:
 
-::
+.. code:: c
 
    typedef void* (*pubsub_cb_t)(const void *arg);
 
@@ -2331,7 +2331,7 @@
 
 -  Define the event ``foo`` in the ``pubsub_events.h``.
 
-   ::
+   .. code:: c
 
       REGISTER_PUBSUB_EVENT(foo);
 
@@ -2467,7 +2467,7 @@
 From outside TF-A, timestamps for individual CPUs can be retrieved by calling
 into ``pmf_smc_handler()``.
 
-.. code:: c
+::
 
     Interface : pmf_smc_handler()
     Argument  : unsigned int smc_fid, u_register_t x1,
@@ -2597,7 +2597,7 @@
 directive by defining ``MARCH32_DIRECTIVE``.
 I.e:
 
-::
+.. code:: make
 
    MARCH32_DIRECTIVE := -mach=armv7-a
 
diff --git a/docs/design/interrupt-framework-design.rst b/docs/design/interrupt-framework-design.rst
index 6f692b2..d4057ea 100644
--- a/docs/design/interrupt-framework-design.rst
+++ b/docs/design/interrupt-framework-design.rst
@@ -48,7 +48,7 @@
 The following constants define the various interrupt types in the framework
 implementation.
 
-::
+.. code:: c
 
     #define INTR_TYPE_S_EL1      0
     #define INTR_TYPE_EL3        1
diff --git a/docs/design/psci-pd-tree.rst b/docs/design/psci-pd-tree.rst
index e52da77..56a6d6f 100644
--- a/docs/design/psci-pd-tree.rst
+++ b/docs/design/psci-pd-tree.rst
@@ -109,7 +109,7 @@
 
 This tree is defined by the platform as the array described above as follows:
 
-::
+.. code:: c
 
         #define PLAT_NUM_POWER_DOMAINS       20
         #define PLATFORM_CORE_COUNT          13
@@ -219,7 +219,7 @@
 The power domain tree is implemented as a combination of the following data
 structures.
 
-::
+.. code:: c
 
     non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
     cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
index 559d701..51e9d3f 100644
--- a/docs/getting_started/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -92,7 +92,7 @@
 the name of the service, the range of OENs covered, the type of service and
 initialization and call handler functions.
 
-::
+.. code:: c
 
     #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch)
 
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
index a4aa1a7..4204027 100644
--- a/docs/getting_started/user-guide.rst
+++ b/docs/getting_started/user-guide.rst
@@ -44,7 +44,7 @@
 
 Install the required packages to build TF-A with the following command:
 
-::
+.. code:: shell
 
     sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
 
@@ -106,14 +106,14 @@
 environment variable to point to ``checkpatch.pl`` (with the other 2 files in
 the same directory) and build the `checkcodebase` target:
 
-::
+.. code:: shell
 
     make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
 
 To just check the style on the files that differ between your local branch and
 the remote master, use:
 
-::
+.. code:: shell
 
     make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
 
@@ -129,13 +129,13 @@
 
    For AArch64:
 
-   ::
+   .. code:: shell
 
        export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
 
    For AArch32:
 
-   ::
+   .. code:: shell
 
        export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
 
@@ -153,7 +153,7 @@
 
    For AArch64 using Arm Compiler 6:
 
-   ::
+   .. code:: shell
 
        export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
        make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
@@ -164,7 +164,7 @@
 
    For AArch64 using clang:
 
-   ::
+   .. code:: shell
 
        export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
        make CC=<path-to-clang>/bin/clang PLAT=<platform> all
@@ -173,13 +173,13 @@
 
    For AArch64:
 
-   ::
+   .. code:: shell
 
        make PLAT=<platform> all
 
    For AArch32:
 
-   ::
+   .. code:: shell
 
        make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
 
@@ -222,7 +222,7 @@
 
 -  Build products for a specific build variant can be removed using:
 
-   ::
+   .. code:: shell
 
        make DEBUG=<D> PLAT=<platform> clean
 
@@ -230,7 +230,7 @@
 
    The build tree can be removed completely using:
 
-   ::
+   .. code:: shell
 
        make realclean
 
@@ -935,7 +935,7 @@
 
 To compile a debug version and make the build more verbose use
 
-::
+.. code:: shell
 
     make PLAT=<platform> DEBUG=1 V=1 all
 
@@ -955,7 +955,7 @@
 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
 ``LDFLAGS``:
 
-.. code:: makefile
+.. code:: shell
 
     CFLAGS='-O0 -gdwarf-2'                                     \
     make PLAT=<platform> DEBUG=1 V=1 all
@@ -996,7 +996,7 @@
 First clean the TF-A build directory to get rid of any previous BL31 binary.
 Then to build the TSP image use:
 
-::
+.. code:: shell
 
     make PLAT=<platform> SPD=tspd all
 
@@ -1024,13 +1024,13 @@
 
 For AArch64:
 
-::
+.. code:: shell
 
     make PLAT=fvp BL33=<path-to>/bl33.bin fip
 
 For AArch32:
 
-::
+.. code:: shell
 
     make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
 
@@ -1046,13 +1046,13 @@
 
 It is recommended to remove old artifacts before building the tool:
 
-::
+.. code:: shell
 
     make -C tools/fiptool clean
 
 Build the tool:
 
-::
+.. code:: shell
 
     make [DEBUG=1] [V=1] fiptool
 
@@ -1067,7 +1067,7 @@
 
 Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
 
-::
+.. code:: shell
 
     ./tools/fiptool/fiptool create \
         --tb-fw build/<platform>/<build-type>/bl2.bin \
@@ -1076,13 +1076,13 @@
 
 Example 2: view the contents of an existing Firmware package:
 
-::
+.. code:: shell
 
     ./tools/fiptool/fiptool info <path-to>/fip.bin
 
 Example 3: update the entries of an existing Firmware package:
 
-::
+.. code:: shell
 
     # Change the BL2 from Debug to Release version
     ./tools/fiptool/fiptool update \
@@ -1091,14 +1091,14 @@
 
 Example 4: unpack all entries from an existing Firmware package:
 
-::
+.. code:: shell
 
     # Images will be unpacked to the working directory
     ./tools/fiptool/fiptool unpack <path-to>/fip.bin
 
 Example 5: remove an entry from an existing Firmware package:
 
-::
+.. code:: shell
 
     ./tools/fiptool/fiptool remove \
         --tb-fw build/<platform>/debug/fip.bin
@@ -1168,7 +1168,7 @@
 
    Example of command line using RSA development keys:
 
-   ::
+   .. code:: shell
 
        MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
        make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1        \
@@ -1225,7 +1225,7 @@
 previous section), but it can also be built separately with the following
 command:
 
-::
+.. code:: shell
 
     make PLAT=<platform> [DEBUG=1] [V=1] certtool
 
@@ -1234,14 +1234,14 @@
 platform must define its IDs within a ``platform_oid.h`` header file for the
 build to succeed.
 
-::
+.. code:: shell
 
     make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
 
 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
 verbose. The following command should be used to obtain help about the tool:
 
-::
+.. code:: shell
 
     ./tools/cert_create/cert_create -h
 
@@ -1270,7 +1270,7 @@
 
 #. Clean the working directory
 
-   ::
+   .. code:: shell
 
        make realclean
 
@@ -1279,7 +1279,7 @@
    Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
    package included in the Linaro release:
 
-   ::
+   .. code:: shell
 
        # Build the fiptool
        make [DEBUG=1] [V=1] fiptool
@@ -1300,7 +1300,7 @@
 
 #. Build TF-A images and create a new FIP for FVP
 
-   ::
+   .. code:: shell
 
        # AArch64
        make PLAT=fvp BL33=nt-fw.bin all fip
@@ -1315,7 +1315,7 @@
    Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
    as a build parameter.
 
-   ::
+   .. code:: shell
 
        make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
 
@@ -1328,13 +1328,13 @@
    -  Before building BL32, the environment variable ``CROSS_COMPILE`` must point
       to the AArch32 Linaro cross compiler.
 
-      ::
+      .. code:: shell
 
           export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
 
    -  Build BL32 in AArch32.
 
-      ::
+      .. code:: shell
 
           make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
           RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
@@ -1349,14 +1349,14 @@
    -  Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
       must point to the AArch64 Linaro cross compiler.
 
-      ::
+      .. code:: shell
 
           export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
 
    -  The following parameters should be used to build BL1 and BL2 in AArch64
       and point to the BL32 file.
 
-      ::
+      .. code:: shell
 
           make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
           BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
@@ -1494,7 +1494,7 @@
 One way to do that is to create an 8-byte file containing all zero bytes using
 the following command:
 
-::
+.. code:: shell
 
     dd if=/dev/zero of=mailbox.dat bs=1 count=8
 
@@ -1564,7 +1564,7 @@
 without a BL33 and prepare to jump to a BL33 image loaded at address
 0x80000000:
 
-::
+.. code:: shell
 
     make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
 
@@ -1579,7 +1579,7 @@
 For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
 address ``0x82000000``, the firmware can be built like this:
 
-::
+.. code:: shell
 
     CROSS_COMPILE=aarch64-linux-gnu-  \
     make PLAT=fvp DEBUG=1             \
@@ -1627,7 +1627,7 @@
 
 And the FVP binary can be run with the following command:
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
     -C pctl.startup=0.0.0.0                                     \
@@ -1801,7 +1801,7 @@
 The following ``Foundation_Platform`` parameters should be used to boot Linux with
 4 CPUs using the AArch64 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/Foundation_Platform                   \
     --cores=4                                       \
@@ -1837,7 +1837,7 @@
 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
 with 8 CPUs using the AArch64 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_RevC-2xAEMv8A                            \
     -C pctl.startup=0.0.0.0                                     \
@@ -1860,7 +1860,7 @@
 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
 with 8 CPUs using the AArch32 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
     -C pctl.startup=0.0.0.0                                     \
@@ -1888,7 +1888,7 @@
 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
 boot Linux with 8 CPUs using the AArch64 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_Cortex-A57x4-A53x4                       \
     -C pctl.startup=0.0.0.0                                     \
@@ -1906,7 +1906,7 @@
 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
 boot Linux with 4 CPUs using the AArch32 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_Cortex-A32x4                             \
     -C pctl.startup=0.0.0.0                                     \
@@ -1924,7 +1924,7 @@
 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
 with 8 CPUs using the AArch64 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_RevC-2xAEMv8A                             \
     -C pctl.startup=0.0.0.0                                      \
@@ -1979,7 +1979,7 @@
 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
 with 8 CPUs using the AArch32 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_AEMv8A-AEMv8A                             \
     -C pctl.startup=0.0.0.0                                      \
@@ -2019,7 +2019,7 @@
 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
 boot Linux with 8 CPUs using the AArch64 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_Cortex-A57x4-A53x4                        \
     -C pctl.startup=0.0.0.0                                      \
@@ -2047,7 +2047,7 @@
 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
 boot Linux with 4 CPUs using the AArch32 build of TF-A.
 
-::
+.. code:: shell
 
     <path-to>/FVP_Base_Cortex-A32x4                             \
     -C pctl.startup=0.0.0.0                                     \
@@ -2096,7 +2096,7 @@
 to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
 on Juno, at the linux shell prompt, issue the following command:
 
-::
+.. code:: shell
 
     echo +10 > /sys/class/rtc/rtc0/wakealarm
     echo -n mem > /sys/power/state
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index caed8bf..b6fd8c8 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -28,7 +28,7 @@
 We used the upstream `TF master as of 31/01/2017`_, building the platform using
 the ``ENABLE_RUNTIME_INSTRUMENTATION`` option:
 
-::
+.. code:: shell
 
     make PLAT=juno ENABLE_RUNTIME_INSTRUMENTATION=1 \
         SCP_BL2=<path/to/scp-fw.bin>                \
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index 46a5f9b..a1e0659 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -24,13 +24,13 @@
 
 To build for machines with an A64 or H5 SoC:
 
-::
+.. code:: shell
 
     make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
 
 To build for machines with an H6 SoC:
 
-::
+.. code:: shell
 
     make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
 
diff --git a/docs/plat/meson-gxbb.rst b/docs/plat/meson-gxbb.rst
index cae11cd..2cd8342 100644
--- a/docs/plat/meson-gxbb.rst
+++ b/docs/plat/meson-gxbb.rst
@@ -15,7 +15,7 @@
 
 In order to build it:
 
-::
+.. code:: shell
 
     CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31
 
diff --git a/docs/plat/meson-gxl.rst b/docs/plat/meson-gxl.rst
index 3c39c9d..c6d8504 100644
--- a/docs/plat/meson-gxl.rst
+++ b/docs/plat/meson-gxl.rst
@@ -15,7 +15,7 @@
 
 In order to build it:
 
-::
+.. code:: shell
 
     CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl
 
diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst
index 30ae97d..4ebe64b 100644
--- a/docs/plat/qemu.rst
+++ b/docs/plat/qemu.rst
@@ -33,13 +33,13 @@
 
 To build:
 
-::
+.. code:: shell
 
     make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu
 
 To start (QEMU v2.6.0):
 
-::
+.. code:: shell
 
     qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57  \
         -kernel Image                           \
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst
index 856882b..930f76c 100644
--- a/docs/process/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -292,7 +292,7 @@
 If ``MY_STRUCT_SIZE`` in the above example were wrong then the compiler would
 emit an error like this:
 
-.. code:: c
+::
 
   my_struct.h:10:1: error: size of array ‘assert_my_struct_size_mismatch’ is negative
 
diff --git a/docs/security_advisories/security-advisory-tfv-3.rst b/docs/security_advisories/security-advisory-tfv-3.rst
index f74ef17..b395f13 100644
--- a/docs/security_advisories/security-advisory-tfv-3.rst
+++ b/docs/security_advisories/security-advisory-tfv-3.rst
@@ -68,7 +68,7 @@
   of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
   ``enable_mmu()`` function:
 
-  .. code:: c
+  ::
 
       sctlr = read_sctlr_el##_el();               \
       sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;       \
diff --git a/docs/security_advisories/security-advisory-tfv-8.rst b/docs/security_advisories/security-advisory-tfv-8.rst
index 5a5ef7c..c401eb3 100644
--- a/docs/security_advisories/security-advisory-tfv-8.rst
+++ b/docs/security_advisories/security-advisory-tfv-8.rst
@@ -39,7 +39,7 @@
 can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
 (referring to the version of the code as of `commit c385955`_):
 
-.. code:: c
+::
 
     /*
      * This function restores all general purpose registers except x30 from the