Merge "TF-A: Redefine true/false definitions" into integration
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index ba087a2..f184b69 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -33,6 +33,7 @@
Target_SoC should be "imx8mq" for i.MX8MQ SoC.
Target_SoC should be "imx8mm" for i.MX8MM SoC.
Target_SoC should be "imx8mn" for i.MX8MN SoC.
+ Target_SoC should be "imx8mp" for i.MX8MP SoC.
Deploy TF-A Images
~~~~~~~~~~~~~~~~~~
diff --git a/drivers/brcm/rng.c b/drivers/brcm/rng.c
new file mode 100644
index 0000000..ee2e656
--- /dev/null
+++ b/drivers/brcm/rng.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2017 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define RNG_CTRL_REG (RNG_BASE_ADDR + 0x00)
+#define RNG_CTRL_MASK 0x00001FFF
+#define RNG_CTRL_ENABLE 0x00000001
+#define RNG_CTRL_DISABLE 0x00000000
+
+#define RNG_SOFT_RESET_REG (RNG_BASE_ADDR + 0x04)
+#define RNG_SOFT_RESET_MASK 0x00000001
+
+#define RNG_FIFO_DATA_REG (RNG_BASE_ADDR + 0x20)
+
+#define RNG_FIFO_COUNT_REG (RNG_BASE_ADDR + 0x24)
+#define RNG_FIFO_COUNT_MASK 0x000000FF
+
+#define RNG_FIFO_WORDS_MAX 16
+#define MAX_WAIT_COUNT_50US 20000
+
+
+static void rng_reset(void)
+{
+ /* Disable RBG */
+ mmio_clrbits_32(RNG_CTRL_REG, RNG_CTRL_MASK);
+
+ /* Reset RNG and RBG */
+ mmio_setbits_32(RNG_SOFT_RESET_REG, RNG_SOFT_RESET_MASK);
+
+ /* Take all out of reset */
+ mmio_clrbits_32(RNG_SOFT_RESET_REG, RNG_SOFT_RESET_MASK);
+}
+
+static void rng_enable(void)
+{
+ /* Setup RNG. */
+ mmio_clrsetbits_32(RNG_CTRL_REG, RNG_CTRL_MASK, RNG_CTRL_ENABLE);
+}
+
+int rng_init(void)
+{
+ rng_reset();
+
+ rng_enable();
+
+ return 0;
+}
+
+int rng_read(uint32_t *p_out, uint32_t *words_read)
+{
+ uint32_t available_words;
+ uint32_t i;
+ uint32_t word_processed = 0;
+ uint32_t wait_count = MAX_WAIT_COUNT_50US;
+
+ if (*words_read == 0) {
+ ERROR("RNG Parameter: No word requested\n");
+ return -1;
+ }
+
+ do {
+ available_words = mmio_read_32(RNG_FIFO_COUNT_REG);
+ available_words &= RNG_FIFO_COUNT_MASK;
+
+ if (available_words != 0) {
+ available_words = MIN(available_words,
+ *words_read - word_processed);
+
+ for (i = 0; i < available_words; i++)
+ p_out[word_processed + i] =
+ mmio_read_32(RNG_FIFO_DATA_REG);
+ word_processed += available_words;
+ } else {
+ udelay(50);
+ }
+
+ if (word_processed == *words_read)
+ break;
+
+ } while (--wait_count);
+
+ if (word_processed != *words_read) {
+ ERROR("RNG Timeout: requested %d word(s) got %d\n",
+ *words_read, word_processed);
+ *words_read = word_processed;
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/drivers/io/io_fip.c b/drivers/io/io_fip.c
index 02f85d6..c11ef11 100644
--- a/drivers/io/io_fip.c
+++ b/drivers/io/io_fip.c
@@ -36,7 +36,7 @@
typedef struct {
unsigned int file_pos;
fip_toc_entry_t entry;
-} file_state_t;
+} fip_file_state_t;
/*
* Maintain dev_spec per FIP Device
@@ -49,7 +49,6 @@
uint16_t plat_toc_flag;
} fip_dev_state_t;
-static const uuid_t uuid_null;
/*
* Only one file can be open across all FIP device
* as backends like io_memmap don't support
@@ -57,7 +56,7 @@
* backend handle should be maintained per FIP device
* if the same support is available in the backend
*/
-static file_state_t current_file = {0};
+static fip_file_state_t current_fip_file = {0};
static uintptr_t backend_dev_handle;
static uintptr_t backend_image_spec;
@@ -288,6 +287,7 @@
int result;
uintptr_t backend_handle;
const io_uuid_spec_t *uuid_spec = (io_uuid_spec_t *)spec;
+ static const uuid_t uuid_null = { {0} }; /* Double braces for clang */
size_t bytes_read;
int found_file = 0;
@@ -300,7 +300,7 @@
* When the system supports dynamic memory allocation we can allow more
* than one open file at a time if needed.
*/
- if (current_file.entry.offset_address != 0) {
+ if (current_fip_file.entry.offset_address != 0U) {
WARN("fip_file_open : Only one open file at a time.\n");
return -ENOMEM;
}
@@ -326,31 +326,32 @@
found_file = 0;
do {
result = io_read(backend_handle,
- (uintptr_t)¤t_file.entry,
- sizeof(current_file.entry),
+ (uintptr_t)¤t_fip_file.entry,
+ sizeof(current_fip_file.entry),
&bytes_read);
if (result == 0) {
- if (compare_uuids(¤t_file.entry.uuid,
+ if (compare_uuids(¤t_fip_file.entry.uuid,
&uuid_spec->uuid) == 0) {
found_file = 1;
- break;
}
} else {
WARN("Failed to read FIP (%i)\n", result);
goto fip_file_open_close;
}
- } while (compare_uuids(¤t_file.entry.uuid, &uuid_null) != 0);
+ } while ((found_file == 0) &&
+ (compare_uuids(¤t_fip_file.entry.uuid,
+ &uuid_null) != 0));
if (found_file == 1) {
/* All fine. Update entity info with file state and return. Set
- * the file position to 0. The 'current_file.entry' holds the
- * base and size of the file.
+ * the file position to 0. The 'current_fip_file.entry' holds
+ * the base and size of the file.
*/
- current_file.file_pos = 0;
- entity->info = (uintptr_t)¤t_file;
+ current_fip_file.file_pos = 0;
+ entity->info = (uintptr_t)¤t_fip_file;
} else {
/* Did not find the file in the FIP. */
- current_file.entry.offset_address = 0;
+ current_fip_file.entry.offset_address = 0;
result = -ENOENT;
}
@@ -368,7 +369,7 @@
assert(entity != NULL);
assert(length != NULL);
- *length = ((file_state_t *)entity->info)->entry.size;
+ *length = ((fip_file_state_t *)entity->info)->entry.size;
return 0;
}
@@ -379,7 +380,7 @@
size_t *length_read)
{
int result;
- file_state_t *fp;
+ fip_file_state_t *fp;
size_t file_offset;
size_t bytes_read;
uintptr_t backend_handle;
@@ -397,7 +398,7 @@
goto fip_file_read_exit;
}
- fp = (file_state_t *)entity->info;
+ fp = (fip_file_state_t *)entity->info;
/* Seek to the position in the FIP where the payload lives */
file_offset = fp->entry.offset_address + fp->file_pos;
@@ -436,8 +437,8 @@
/* Clear our current file pointer.
* If we had malloc() we would free() here.
*/
- if (current_file.entry.offset_address != 0) {
- zeromem(¤t_file, sizeof(current_file));
+ if (current_fip_file.entry.offset_address != 0U) {
+ zeromem(¤t_fip_file, sizeof(current_fip_file));
}
/* Clear the Entity info. */
diff --git a/drivers/io/io_memmap.c b/drivers/io/io_memmap.c
index eed50cc..eb69163 100644
--- a/drivers/io/io_memmap.c
+++ b/drivers/io/io_memmap.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,9 +27,9 @@
uintptr_t base;
unsigned long long file_pos;
unsigned long long size;
-} file_state_t;
+} memmap_file_state_t;
-static file_state_t current_file = {0};
+static memmap_file_state_t current_memmap_file = {0};
/* Identify the device type as memmap */
static io_type_t device_type_memmap(void)
@@ -71,7 +71,7 @@
/* No state associated with this device so structure can be const */
-static const io_dev_info_t memmap_dev_info = {
+static io_dev_info_t memmap_dev_info = {
.funcs = &memmap_dev_funcs,
.info = (uintptr_t)NULL
};
@@ -82,8 +82,7 @@
io_dev_info_t **dev_info)
{
assert(dev_info != NULL);
- *dev_info = (io_dev_info_t *)&memmap_dev_info; /* cast away const */
-
+ *dev_info = &memmap_dev_info;
return 0;
}
@@ -109,16 +108,16 @@
* spec at a time. When we have dynamic memory we can malloc and set
* entity->info.
*/
- if (current_file.in_use == 0) {
+ if (current_memmap_file.in_use == 0) {
assert(block_spec != NULL);
assert(entity != NULL);
- current_file.in_use = 1;
- current_file.base = block_spec->offset;
+ current_memmap_file.in_use = 1;
+ current_memmap_file.base = block_spec->offset;
/* File cursor offset for seek and incremental reads etc. */
- current_file.file_pos = 0;
- current_file.size = block_spec->length;
- entity->info = (uintptr_t)¤t_file;
+ current_memmap_file.file_pos = 0;
+ current_memmap_file.size = block_spec->length;
+ entity->info = (uintptr_t)¤t_memmap_file;
result = 0;
} else {
WARN("A Memmap device is already active. Close first.\n");
@@ -133,13 +132,13 @@
signed long long offset)
{
int result = -ENOENT;
- file_state_t *fp;
+ memmap_file_state_t *fp;
/* We only support IO_SEEK_SET for the moment. */
if (mode == IO_SEEK_SET) {
assert(entity != NULL);
- fp = (file_state_t *) entity->info;
+ fp = (memmap_file_state_t *) entity->info;
/* Assert that new file position is valid */
assert((offset >= 0) &&
@@ -160,7 +159,7 @@
assert(entity != NULL);
assert(length != NULL);
- *length = (size_t)((file_state_t *)entity->info)->size;
+ *length = (size_t)((memmap_file_state_t *)entity->info)->size;
return 0;
}
@@ -170,13 +169,13 @@
static int memmap_block_read(io_entity_t *entity, uintptr_t buffer,
size_t length, size_t *length_read)
{
- file_state_t *fp;
+ memmap_file_state_t *fp;
unsigned long long pos_after;
assert(entity != NULL);
assert(length_read != NULL);
- fp = (file_state_t *) entity->info;
+ fp = (memmap_file_state_t *) entity->info;
/* Assert that file position is valid for this read operation */
pos_after = fp->file_pos + length;
@@ -198,13 +197,13 @@
static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer,
size_t length, size_t *length_written)
{
- file_state_t *fp;
+ memmap_file_state_t *fp;
unsigned long long pos_after;
assert(entity != NULL);
assert(length_written != NULL);
- fp = (file_state_t *) entity->info;
+ fp = (memmap_file_state_t *) entity->info;
/* Assert that file position is valid for this write operation */
pos_after = fp->file_pos + length;
@@ -230,7 +229,7 @@
entity->info = 0;
/* This would be a mem free() if we had malloc.*/
- zeromem((void *)¤t_file, sizeof(current_file));
+ zeromem((void *)¤t_memmap_file, sizeof(current_memmap_file));
return 0;
}
diff --git a/drivers/io/io_semihosting.c b/drivers/io/io_semihosting.c
index 4ceddc6..1c2f84d 100644
--- a/drivers/io/io_semihosting.c
+++ b/drivers/io/io_semihosting.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,8 +51,7 @@
};
-/* No state associated with this device so structure can be const */
-static const io_dev_info_t sh_dev_info = {
+static io_dev_info_t sh_dev_info = {
.funcs = &sh_dev_funcs,
.info = (uintptr_t)NULL
};
@@ -63,7 +62,7 @@
io_dev_info_t **dev_info)
{
assert(dev_info != NULL);
- *dev_info = (io_dev_info_t *)&sh_dev_info; /* cast away const */
+ *dev_info = &sh_dev_info;
return 0;
}
diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c
index ba6f094..0534268 100644
--- a/drivers/io/io_storage.c
+++ b/drivers/io/io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,14 +32,13 @@
#if ENABLE_ASSERTIONS
/* Return a boolean value indicating whether a device connector is valid */
-static int is_valid_dev_connector(const io_dev_connector_t *dev_con)
+static bool is_valid_dev_connector(const io_dev_connector_t *dev_con)
{
return (dev_con != NULL) && (dev_con->dev_open != NULL);
}
-
/* Return a boolean value indicating whether a device handle is valid */
-static int is_valid_dev(const uintptr_t dev_handle)
+static bool is_valid_dev(const uintptr_t dev_handle)
{
const io_dev_info_t *dev = (io_dev_info_t *)dev_handle;
@@ -50,7 +49,7 @@
/* Return a boolean value indicating whether an IO entity is valid */
-static int is_valid_entity(const uintptr_t handle)
+static bool is_valid_entity(const uintptr_t handle)
{
const io_entity_t *entity = (io_entity_t *)handle;
@@ -60,7 +59,7 @@
/* Return a boolean value indicating whether a seek mode is valid */
-static int is_valid_seek_mode(io_seek_mode_t mode)
+static bool is_valid_seek_mode(io_seek_mode_t mode)
{
return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX));
}
@@ -70,7 +69,8 @@
/* Open a connection to a specific device */
-static int dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec,
+static int io_storage_dev_open(const io_dev_connector_t *dev_con,
+ const uintptr_t dev_spec,
io_dev_info_t **dev_info)
{
assert(dev_info != NULL);
@@ -113,7 +113,8 @@
unsigned int index = 0;
result = find_first_entity(NULL, &index);
assert(result == 0);
- *entity = entity_map[index] = &entity_pool[index];
+ *entity = &entity_pool[index];
+ entity_map[index] = &entity_pool[index];
++entity_count;
}
@@ -161,8 +162,7 @@
uintptr_t *handle)
{
assert(handle != NULL);
-
- return dev_open(dev_con, dev_spec, (io_dev_info_t **)handle);
+ return io_storage_dev_open(dev_con, dev_spec, (io_dev_info_t **)handle);
}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 2f4dcad..d6cd8b1 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -577,6 +577,43 @@
1, 2, 3, 4, 4, 4, 4, 4
};
+static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = {
+ [_HSI] = "HSI",
+ [_HSE] = "HSE",
+ [_CSI] = "CSI",
+ [_LSI] = "LSI",
+ [_LSE] = "LSE",
+ [_I2S_CKIN] = "I2S_CKIN",
+ [_HSI_KER] = "HSI_KER",
+ [_HSE_KER] = "HSE_KER",
+ [_HSE_KER_DIV2] = "HSE_KER_DIV2",
+ [_CSI_KER] = "CSI_KER",
+ [_PLL1_P] = "PLL1_P",
+ [_PLL1_Q] = "PLL1_Q",
+ [_PLL1_R] = "PLL1_R",
+ [_PLL2_P] = "PLL2_P",
+ [_PLL2_Q] = "PLL2_Q",
+ [_PLL2_R] = "PLL2_R",
+ [_PLL3_P] = "PLL3_P",
+ [_PLL3_Q] = "PLL3_Q",
+ [_PLL3_R] = "PLL3_R",
+ [_PLL4_P] = "PLL4_P",
+ [_PLL4_Q] = "PLL4_Q",
+ [_PLL4_R] = "PLL4_R",
+ [_ACLK] = "ACLK",
+ [_PCLK1] = "PCLK1",
+ [_PCLK2] = "PCLK2",
+ [_PCLK3] = "PCLK3",
+ [_PCLK4] = "PCLK4",
+ [_PCLK5] = "PCLK5",
+ [_HCLK6] = "KCLK6",
+ [_HCLK2] = "HCLK2",
+ [_CK_PER] = "CK_PER",
+ [_CK_MPU] = "CK_MPU",
+ [_CK_MCU] = "CK_MCU",
+ [_USB_PHY_48] = "USB_PHY_48",
+};
+
/* RCC clock device driver private */
static unsigned long stm32mp1_osc[NB_OSC];
static struct spinlock reg_lock;
@@ -2007,6 +2044,165 @@
}
}
+#ifdef STM32MP_SHARED_RESOURCES
+/*
+ * Get the parent ID of the target parent clock, for tagging as secure
+ * shared clock dependencies.
+ */
+static int get_parent_id_parent(unsigned int parent_id)
+{
+ enum stm32mp1_parent_sel s = _UNKNOWN_SEL;
+ enum stm32mp1_pll_id pll_id;
+ uint32_t p_sel;
+ uintptr_t rcc_base = stm32mp_rcc_base();
+
+ switch (parent_id) {
+ case _ACLK:
+ case _PCLK4:
+ case _PCLK5:
+ s = _AXIS_SEL;
+ break;
+ case _PLL1_P:
+ case _PLL1_Q:
+ case _PLL1_R:
+ pll_id = _PLL1;
+ break;
+ case _PLL2_P:
+ case _PLL2_Q:
+ case _PLL2_R:
+ pll_id = _PLL2;
+ break;
+ case _PLL3_P:
+ case _PLL3_Q:
+ case _PLL3_R:
+ pll_id = _PLL3;
+ break;
+ case _PLL4_P:
+ case _PLL4_Q:
+ case _PLL4_R:
+ pll_id = _PLL4;
+ break;
+ case _PCLK1:
+ case _PCLK2:
+ case _HCLK2:
+ case _HCLK6:
+ case _CK_PER:
+ case _CK_MPU:
+ case _CK_MCU:
+ case _USB_PHY_48:
+ /* We do not expect to access these */
+ panic();
+ break;
+ default:
+ /* Other parents have no parent */
+ return -1;
+ }
+
+ if (s != _UNKNOWN_SEL) {
+ const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);
+
+ p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &
+ sel->msk;
+
+ if (p_sel < sel->nb_parent) {
+ return (int)sel->parent[p_sel];
+ }
+ } else {
+ const struct stm32mp1_clk_pll *pll = pll_ref(pll_id);
+
+ p_sel = mmio_read_32(rcc_base + pll->rckxselr) &
+ RCC_SELR_REFCLK_SRC_MASK;
+
+ if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) {
+ return (int)pll->refclk[p_sel];
+ }
+ }
+
+ VERBOSE("No parent selected for %s\n",
+ stm32mp1_clk_parent_name[parent_id]);
+
+ return -1;
+}
+
+static void secure_parent_clocks(unsigned long parent_id)
+{
+ int grandparent_id;
+
+ switch (parent_id) {
+ case _PLL3_P:
+ case _PLL3_Q:
+ case _PLL3_R:
+ stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
+ break;
+
+ /* These clocks are always secure when RCC is secure */
+ case _ACLK:
+ case _HCLK2:
+ case _HCLK6:
+ case _PCLK4:
+ case _PCLK5:
+ case _PLL1_P:
+ case _PLL1_Q:
+ case _PLL1_R:
+ case _PLL2_P:
+ case _PLL2_Q:
+ case _PLL2_R:
+ case _HSI:
+ case _HSI_KER:
+ case _LSI:
+ case _CSI:
+ case _CSI_KER:
+ case _HSE:
+ case _HSE_KER:
+ case _HSE_KER_DIV2:
+ case _LSE:
+ break;
+
+ default:
+ VERBOSE("Cannot secure parent clock %s\n",
+ stm32mp1_clk_parent_name[parent_id]);
+ panic();
+ }
+
+ grandparent_id = get_parent_id_parent(parent_id);
+ if (grandparent_id >= 0) {
+ secure_parent_clocks(grandparent_id);
+ }
+}
+
+void stm32mp1_register_clock_parents_secure(unsigned long clock_id)
+{
+ int parent_id;
+
+ if (!stm32mp1_rcc_is_secure()) {
+ return;
+ }
+
+ switch (clock_id) {
+ case PLL1:
+ case PLL2:
+ /* PLL1/PLL2 are always secure: nothing to do */
+ break;
+ case PLL3:
+ stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3);
+ break;
+ case PLL4:
+ ERROR("PLL4 cannot be secured\n");
+ panic();
+ break;
+ default:
+ /* Others are expected gateable clock */
+ parent_id = stm32mp1_clk_get_parent(clock_id);
+ if (parent_id < 0) {
+ INFO("No parent found for clock %lu\n", clock_id);
+ } else {
+ secure_parent_clocks(parent_id);
+ }
+ break;
+ }
+}
+#endif /* STM32MP_SHARED_RESOURCES */
+
static void sync_earlyboot_clocks_state(void)
{
unsigned int idx;
diff --git a/drivers/st/crypto/stm32_hash.c b/drivers/st/crypto/stm32_hash.c
index 3184df9..515947c 100644
--- a/drivers/st/crypto/stm32_hash.c
+++ b/drivers/st/crypto/stm32_hash.c
@@ -300,7 +300,9 @@
break;
}
#else
+ /* BL32 uses hash if it is assigned only to secure world */
if (hash_info.status == DT_SECURE) {
+ stm32mp_register_secure_periph_iomem(hash_info.base);
break;
}
#endif
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index a13c341..bb77371 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -254,6 +254,15 @@
mmio_read_32(base + GPIO_AFRH_OFFSET));
stm32mp_clk_disable(clock);
+
+ if (status == DT_SECURE) {
+ stm32mp_register_secure_gpio(bank, pin);
+ set_gpio_secure_cfg(bank, pin, true);
+
+ } else {
+ stm32mp_register_non_secure_gpio(bank, pin);
+ set_gpio_secure_cfg(bank, pin, false);
+ }
}
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index ea6fbb2..c052b4d 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c
@@ -137,6 +137,12 @@
((dt_info.status & DT_NON_SECURE) != 0) ?
"non-" : "");
+ if ((dt_info.status & DT_NON_SECURE) != 0) {
+ stm32mp_register_non_secure_periph_iomem(iwdg->base);
+ } else {
+ stm32mp_register_secure_periph_iomem(iwdg->base);
+ }
+
#if defined(IMAGE_BL2)
if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) {
return -1;
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 9e9dddc..b2bb482 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -54,6 +54,15 @@
return fdt_get_status(node);
}
+static bool dt_pmic_is_secure(void)
+{
+ int status = dt_pmic_status();
+
+ return (status >= 0) &&
+ (status == DT_SECURE) &&
+ (i2c_handle.dt_status == DT_SECURE);
+}
+
/*
* Get PMIC and its I2C bus configuration from the device tree.
* Return 0 on success, negative on error, 1 if no PMIC node is found.
@@ -223,6 +232,19 @@
return true;
}
+static void register_pmic_shared_peripherals(void)
+{
+ uintptr_t i2c_base = i2c_handle.i2c_base_addr;
+
+ if (dt_pmic_is_secure()) {
+ stm32mp_register_secure_periph_iomem(i2c_base);
+ } else {
+ if (i2c_base != 0U) {
+ stm32mp_register_non_secure_periph_iomem(i2c_base);
+ }
+ }
+}
+
void initialize_pmic(void)
{
unsigned long pmic_version;
@@ -232,6 +254,8 @@
return;
}
+ register_pmic_shared_peripherals();
+
if (stpmic1_get_version(&pmic_version) != 0) {
ERROR("Failed to access PMIC\n");
panic();
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index 1d8da18..a571092 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -9,6 +9,8 @@
#ifndef FDT_WRAPPERS_H
#define FDT_WRAPPERS_H
+#include <libfdt_env.h>
+
/* Number of cells, given total length in bytes. Each cell is 4 bytes long */
#define NCELLS(len) ((len) / 4U)
@@ -37,4 +39,11 @@
uint64_t fdtw_translate_address(const void *dtb, int bus_node,
uint64_t base_address);
+static inline uint32_t fdt_blob_size(const void *dtb)
+{
+ const uint32_t *dtb_header = dtb;
+
+ return fdt32_to_cpu(dtb_header[1]);
+}
+
#endif /* FDT_WRAPPERS_H */
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
index 1ebd39f..c46892b 100644
--- a/include/drivers/st/stm32mp1_clk.h
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -59,4 +59,7 @@
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
+#ifdef STM32MP_SHARED_RESOURCES
+void stm32mp1_register_clock_parents_secure(unsigned long id);
+#endif
#endif /* STM32MP1_CLK_H */
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
index 0378729..5f1951f 100644
--- a/plat/arm/board/arm_fpga/fpga_def.h
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -18,7 +18,7 @@
* that are present will still be indexed appropriately regardless of any empty
* entries in the array used to represent the topology.
*/
-#define FPGA_MAX_CLUSTER_COUNT 2
+#define FPGA_MAX_CLUSTER_COUNT 4
#define FPGA_MAX_CPUS_PER_CLUSTER 8
#define FPGA_MAX_PE_PER_CPU 4
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 34e50ea..e57912c 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -24,15 +24,10 @@
$(error "TRUSTED_BOARD_BOOT must be disabled")
endif
-ifndef PRELOADED_BL33_BASE
-$(error "PRELOADED_BL33_BASE is not set")
-endif
+PRELOADED_BL33_BASE := 0x80080000
-ifndef FPGA_PRELOADED_DTB_BASE
-$(error "FPGA_PRELOADED_DTB_BASE is not set")
-else
+FPGA_PRELOADED_DTB_BASE := 0x80070000
$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
-endif
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
@@ -64,7 +59,10 @@
lib/cpus/aarch64/neoverse_zeus.S \
lib/cpus/aarch64/cortex_hercules_ae.S \
lib/cpus/aarch64/cortex_a65.S \
- lib/cpus/aarch64/cortex_a65ae.S
+ lib/cpus/aarch64/cortex_a65ae.S \
+ lib/cpus/aarch64/cortex_klein.S \
+ lib/cpus/aarch64/cortex_matterhorn.S
+
# AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S
diff --git a/plat/brcm/board/common/board_common.mk b/plat/brcm/board/common/board_common.mk
index 808a107..3069f91 100644
--- a/plat/brcm/board/common/board_common.mk
+++ b/plat/brcm/board/common/board_common.mk
@@ -133,6 +133,12 @@
plat/brcm/board/common/sbl_util.c \
drivers/arm/sp805/sp805.c
+# Add RNG driver
+DRIVER_RNG_ENABLE := 1
+ifeq (${DRIVER_RNG_ENABLE},1)
+PLAT_BL_COMMON_SOURCES += drivers/brcm/rng.c
+endif
+
# Add eMMC driver
ifeq (${DRIVER_EMMC_ENABLE},1)
$(eval $(call add_define,DRIVER_EMMC_ENABLE))
diff --git a/plat/brcm/board/stingray/include/sr_def.h b/plat/brcm/board/stingray/include/sr_def.h
index ac3ee78..be0dee1 100644
--- a/plat/brcm/board/stingray/include/sr_def.h
+++ b/plat/brcm/board/stingray/include/sr_def.h
@@ -292,6 +292,11 @@
#define ICFG_PKA_MEM_PWR_CTRL__ISO BIT(8)
/*******************************************************************************
+ * RNG constants
+ ******************************************************************************/
+#define RNG_BASE_ADDR 0x68b20000
+
+/*******************************************************************************
* Trusted Watchdog constants
******************************************************************************/
#define ARM_SP805_TWDG_BASE 0x68b30000
diff --git a/plat/imx/imx8m/imx8mm/include/gpc_reg.h b/plat/imx/imx8m/imx8mm/include/gpc_reg.h
new file mode 100644
index 0000000..c697af2
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/include/gpc_reg.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPC_REG_H
+#define GPC_REG_H
+
+#define LPCR_A53_BSC 0x0
+#define LPCR_A53_BSC2 0x108
+#define LPCR_A53_AD 0x4
+#define LPCR_M4 0x8
+#define SLPCR 0x14
+#define MST_CPU_MAPPING 0x18
+#define MLPCR 0x20
+#define PGC_ACK_SEL_A53 0x24
+#define IMR1_CORE0_A53 0x30
+#define IMR1_CORE1_A53 0x40
+#define IMR1_CORE2_A53 0x1C0
+#define IMR1_CORE3_A53 0x1D0
+#define IMR1_CORE0_M4 0x50
+#define SLT0_CFG 0xB0
+#define GPC_PU_PWRHSK 0x1FC
+#define PGC_CPU_0_1_MAPPING 0xEC
+#define CPU_PGC_UP_TRG 0xF0
+#define PU_PGC_UP_TRG 0xF8
+#define CPU_PGC_DN_TRG 0xFC
+#define PU_PGC_DN_TRG 0x104
+#define LPS_CPU1 0x114
+#define A53_CORE0_PGC 0x800
+#define A53_PLAT_PGC 0x900
+#define PLAT_PGC_PCR 0x900
+#define NOC_PGC_PCR 0xa40
+#define PGC_SCU_TIMING 0x910
+
+#define MASK_DSM_TRIGGER_A53 BIT(31)
+#define IRQ_SRC_A53_WUP BIT(30)
+#define IRQ_SRC_A53_WUP_SHIFT 30
+#define IRQ_SRC_C1 BIT(29)
+#define IRQ_SRC_C0 BIT(28)
+#define IRQ_SRC_C3 BIT(23)
+#define IRQ_SRC_C2 BIT(22)
+#define CPU_CLOCK_ON_LPM BIT(14)
+#define A53_CLK_ON_LPM BIT(14)
+#define MASTER0_LPM_HSK BIT(6)
+#define MASTER1_LPM_HSK BIT(7)
+#define MASTER2_LPM_HSK BIT(8)
+
+#define L2PGE BIT(31)
+#define EN_L2_WFI_PDN BIT(5)
+#define EN_PLAT_PDN BIT(4)
+
+#define SLPCR_EN_DSM BIT(31)
+#define SLPCR_RBC_EN BIT(30)
+#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
+#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
+#define SLPCR_VSTBY BIT(2)
+#define SLPCR_SBYOS BIT(1)
+#define SLPCR_BYPASS_PMIC_READY BIT(0)
+#define SLPCR_RBC_COUNT_SHIFT 24
+#define SLPCR_STBY_COUNT_SHFT 3
+
+#define A53_DUMMY_PDN_ACK BIT(15)
+#define A53_DUMMY_PUP_ACK BIT(31)
+#define A53_PLAT_PDN_ACK BIT(2)
+#define A53_PLAT_PUP_ACK BIT(18)
+#define NOC_PDN_SLT_CTRL BIT(10)
+#define NOC_PUP_SLT_CTRL BIT(11)
+#define NOC_PGC_PDN_ACK BIT(3)
+#define NOC_PGC_PUP_ACK BIT(19)
+
+#define PLAT_PUP_SLT_CTRL BIT(9)
+#define PLAT_PDN_SLT_CTRL BIT(8)
+
+#define SLT_PLAT_PDN BIT(8)
+#define SLT_PLAT_PUP BIT(9)
+
+#define MASTER1_MAPPING BIT(1)
+#define MASTER2_MAPPING BIT(2)
+
+#define MIPI_PWR_REQ BIT(0)
+#define PCIE_PWR_REQ BIT(1)
+#define OTG1_PWR_REQ BIT(2)
+#define OTG2_PWR_REQ BIT(3)
+#define HSIOMIX_PWR_REQ BIT(4)
+#define DDRMIX_PWR_REQ BIT(5)
+#define GPU2D_PWR_REQ BIT(6)
+#define GPUMIX_PWR_REQ BIT(7)
+#define VPUMIX_PWR_REQ BIT(8)
+#define GPU3D_PWR_REQ BIT(9)
+#define DISPMIX_PWR_REQ BIT(10)
+#define VPU_G1_PWR_REQ BIT(11)
+#define VPU_G2_PWR_REQ BIT(12)
+#define VPU_H1_PWR_REQ BIT(13)
+
+#define DDRMIX_ADB400_SYNC BIT(2)
+#define HSIOMIX_ADB400_SYNC (0x3 << 5)
+#define DISPMIX_ADB400_SYNC BIT(7)
+#define VPUMIX_ADB400_SYNC BIT(8)
+#define GPU3D_ADB400_SYNC BIT(9)
+#define GPU2D_ADB400_SYNC BIT(10)
+#define GPUMIX_ADB400_SYNC BIT(11)
+#define DDRMIX_ADB400_ACK BIT(20)
+#define HSIOMIX_ADB400_ACK (0x3 << 23)
+#define DISPMIX_ADB400_ACK BIT(25)
+#define VPUMIX_ADB400_ACK BIT(26)
+#define GPU3D_ADB400_ACK BIT(27)
+#define GPU2D_ADB400_ACK BIT(28)
+#define GPUMIX_ADB400_ACK BIT(29)
+
+#define MIPI_PGC 0xc00
+#define PCIE_PGC 0xc40
+#define OTG1_PGC 0xc80
+#define OTG2_PGC 0xcc0
+#define HSIOMIX_PGC 0xd00
+#define DDRMIX_PGC 0xd40
+#define GPU2D_PGC 0xd80
+#define GPUMIX_PGC 0xdc0
+#define VPUMIX_PGC 0xe00
+#define GPU3D_PGC 0xe40
+#define DISPMIX_PGC 0xe80
+#define VPU_G1_PGC 0xec0
+#define VPU_G2_PGC 0xf00
+#define VPU_H1_PGC 0xf40
+
+#endif /* GPC_REG_H */
diff --git a/plat/imx/imx8m/imx8mn/include/gpc_reg.h b/plat/imx/imx8m/imx8mn/include/gpc_reg.h
new file mode 100644
index 0000000..fd10438
--- /dev/null
+++ b/plat/imx/imx8m/imx8mn/include/gpc_reg.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPC_REG_H
+#define GPC_REG_H
+
+#define LPCR_A53_BSC 0x0
+#define LPCR_A53_BSC2 0x108
+#define LPCR_A53_AD 0x4
+#define LPCR_M4 0x8
+#define SLPCR 0x14
+#define MST_CPU_MAPPING 0x18
+#define MLPCR 0x20
+#define PGC_ACK_SEL_A53 0x24
+#define IMR1_CORE0_A53 0x30
+#define IMR1_CORE1_A53 0x40
+#define IMR1_CORE2_A53 0x1C0
+#define IMR1_CORE3_A53 0x1D0
+#define IMR1_CORE0_M4 0x50
+#define SLT0_CFG 0xB0
+#define GPC_PU_PWRHSK 0x1FC
+#define PGC_CPU_0_1_MAPPING 0xEC
+#define CPU_PGC_UP_TRG 0xF0
+#define PU_PGC_UP_TRG 0xF8
+#define CPU_PGC_DN_TRG 0xFC
+#define PU_PGC_DN_TRG 0x104
+#define LPS_CPU1 0x114
+#define A53_CORE0_PGC 0x800
+#define A53_PLAT_PGC 0x900
+#define PLAT_PGC_PCR 0x900
+#define NOC_PGC_PCR 0xa40
+#define PGC_SCU_TIMING 0x910
+
+#define MASK_DSM_TRIGGER_A53 BIT(31)
+#define IRQ_SRC_A53_WUP BIT(30)
+#define IRQ_SRC_A53_WUP_SHIFT 30
+#define IRQ_SRC_C1 BIT(29)
+#define IRQ_SRC_C0 BIT(28)
+#define IRQ_SRC_C3 BIT(23)
+#define IRQ_SRC_C2 BIT(22)
+#define CPU_CLOCK_ON_LPM BIT(14)
+#define A53_CLK_ON_LPM BIT(14)
+#define MASTER0_LPM_HSK BIT(6)
+#define MASTER1_LPM_HSK BIT(7)
+#define MASTER2_LPM_HSK BIT(8)
+
+#define L2PGE BIT(31)
+#define EN_L2_WFI_PDN BIT(5)
+#define EN_PLAT_PDN BIT(4)
+
+#define SLPCR_EN_DSM BIT(31)
+#define SLPCR_RBC_EN BIT(30)
+#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
+#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
+#define SLPCR_VSTBY BIT(2)
+#define SLPCR_SBYOS BIT(1)
+#define SLPCR_BYPASS_PMIC_READY BIT(0)
+#define SLPCR_RBC_COUNT_SHIFT 24
+#define SLPCR_STBY_COUNT_SHFT 3
+
+#define A53_DUMMY_PDN_ACK BIT(15)
+#define A53_DUMMY_PUP_ACK BIT(31)
+#define A53_PLAT_PDN_ACK BIT(2)
+#define A53_PLAT_PUP_ACK BIT(18)
+#define NOC_PDN_SLT_CTRL BIT(10)
+#define NOC_PUP_SLT_CTRL BIT(11)
+#define NOC_PGC_PDN_ACK BIT(3)
+#define NOC_PGC_PUP_ACK BIT(19)
+
+#define PLAT_PUP_SLT_CTRL BIT(9)
+#define PLAT_PDN_SLT_CTRL BIT(8)
+
+#define SLT_PLAT_PDN BIT(8)
+#define SLT_PLAT_PUP BIT(9)
+
+#define MASTER1_MAPPING BIT(1)
+#define MASTER2_MAPPING BIT(2)
+
+#define TMR_TCD2_SHIFT 0
+#define TMC_TMR_SHIFT 10
+#define TRC1_TMC_SHIFT 20
+
+#define MIPI_PWR_REQ BIT(0)
+#define OTG1_PWR_REQ BIT(2)
+#define HSIOMIX_PWR_REQ BIT(4)
+#define DDRMIX_PWR_REQ BIT(5)
+#define GPUMIX_PWR_REQ BIT(7)
+#define DISPMIX_PWR_REQ BIT(10)
+
+#define DDRMIX_ADB400_SYNC BIT(2)
+#define HSIOMIX_ADB400_SYNC BIT(5)
+#define DISPMIX_ADB400_SYNC BIT(7)
+#define GPUMIX_ADB400_SYNC (0x5 << 9)
+#define DDRMIX_ADB400_ACK BIT(20)
+#define HSIOMIX_ADB400_ACK BIT(23)
+#define DISPMIX_ADB400_ACK BIT(25)
+#define GPUMIX_ADB400_ACK (0x5 << 27)
+
+#define MIPI_PGC 0xc00
+#define OTG1_PGC 0xc80
+#define HSIOMIX_PGC 0xd00
+#define DDRMIX_PGC 0xd40
+#define GPUMIX_PGC 0xdc0
+#define DISPMIX_PGC 0xe80
+
+#endif /* GPC_REG_H */
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
new file mode 100644
index 0000000..d660e3d
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2019-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <lib/smccc.h>
+#include <services/std_svc.h>
+
+#include <gpc.h>
+#include <imx_aipstz.h>
+#include <imx_sip_svc.h>
+#include <platform_def.h>
+
+#define CCGR(x) (0x4000 + (x) * 0x10)
+#define IMR_NUM U(5)
+
+struct imx_noc_setting {
+ uint32_t domain_id;
+ uint32_t start;
+ uint32_t end;
+ uint32_t prioriy;
+ uint32_t mode;
+ uint32_t socket_qos_en;
+};
+
+enum clk_type {
+ CCM_ROOT_SLICE,
+ CCM_CCGR,
+};
+
+struct clk_setting {
+ uint32_t offset;
+ uint32_t val;
+ enum clk_type type;
+};
+
+enum pu_domain_id {
+ /* hsio ss */
+ HSIOMIX,
+ PCIE_PHY,
+ USB1_PHY,
+ USB2_PHY,
+ MLMIX,
+ AUDIOMIX,
+ /* gpu ss */
+ GPUMIX,
+ GPU2D,
+ GPU3D,
+ /* vpu ss */
+ VPUMIX,
+ VPU_G1,
+ VPU_G2,
+ VPU_H1,
+ /* media ss */
+ MEDIAMIX,
+ MEDIAMIX_ISPDWP,
+ MIPI_PHY1,
+ MIPI_PHY2,
+ /* HDMI ss */
+ HDMIMIX,
+ HDMI_PHY,
+ DDRMIX,
+};
+
+/* PU domain, add some hole to minimize the uboot change */
+static struct imx_pwr_domain pu_domains[20] = {
+ [MIPI_PHY1] = IMX_PD_DOMAIN(MIPI_PHY1, false),
+ [PCIE_PHY] = IMX_PD_DOMAIN(PCIE_PHY, false),
+ [USB1_PHY] = IMX_PD_DOMAIN(USB1_PHY, true),
+ [USB2_PHY] = IMX_PD_DOMAIN(USB2_PHY, true),
+ [MLMIX] = IMX_MIX_DOMAIN(MLMIX, false),
+ [AUDIOMIX] = IMX_MIX_DOMAIN(AUDIOMIX, false),
+ [GPU2D] = IMX_PD_DOMAIN(GPU2D, false),
+ [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false),
+ [VPUMIX] = IMX_MIX_DOMAIN(VPUMIX, false),
+ [GPU3D] = IMX_PD_DOMAIN(GPU3D, false),
+ [MEDIAMIX] = IMX_MIX_DOMAIN(MEDIAMIX, false),
+ [VPU_G1] = IMX_PD_DOMAIN(VPU_G1, false),
+ [VPU_G2] = IMX_PD_DOMAIN(VPU_G2, false),
+ [VPU_H1] = IMX_PD_DOMAIN(VPU_H1, false),
+ [HDMIMIX] = IMX_MIX_DOMAIN(HDMIMIX, false),
+ [HDMI_PHY] = IMX_PD_DOMAIN(HDMI_PHY, false),
+ [MIPI_PHY2] = IMX_PD_DOMAIN(MIPI_PHY2, false),
+ [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false),
+ [MEDIAMIX_ISPDWP] = IMX_PD_DOMAIN(MEDIAMIX_ISPDWP, false),
+};
+
+static struct imx_noc_setting noc_setting[] = {
+ {MLMIX, 0x180, 0x180, 0x80000303, 0x0, 0x0},
+ {AUDIOMIX, 0x200, 0x200, 0x80000303, 0x0, 0x0},
+ {AUDIOMIX, 0x280, 0x480, 0x80000404, 0x0, 0x0},
+ {GPUMIX, 0x500, 0x580, 0x80000303, 0x0, 0x0},
+ {HDMIMIX, 0x600, 0x680, 0x80000202, 0x0, 0x1},
+ {HDMIMIX, 0x700, 0x700, 0x80000505, 0x0, 0x0},
+ {HSIOMIX, 0x780, 0x900, 0x80000303, 0x0, 0x0},
+ {MEDIAMIX, 0x980, 0xb80, 0x80000202, 0x0, 0x1},
+ {MEDIAMIX_ISPDWP, 0xc00, 0xd00, 0x80000505, 0x0, 0x0},
+ {VPU_G1, 0xd80, 0xd80, 0x80000303, 0x0, 0x0},
+ {VPU_G2, 0xe00, 0xe00, 0x80000303, 0x0, 0x0},
+ {VPU_H1, 0xe80, 0xe80, 0x80000303, 0x0, 0x0}
+};
+
+static struct clk_setting hsiomix_clk[] = {
+ { 0x8380, 0x0, CCM_ROOT_SLICE },
+ { 0x44d0, 0x0, CCM_CCGR },
+ { 0x45c0, 0x0, CCM_CCGR },
+};
+
+static struct aipstz_cfg aipstz5[] = {
+ {IMX_AIPSTZ5, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
+static unsigned int pu_domain_status;
+
+static void imx_noc_qos(unsigned int domain_id)
+{
+ unsigned int i;
+ uint32_t hurry;
+
+ if (domain_id == HDMIMIX) {
+ mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018);
+ mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010);
+
+ /* set GPR to make lcdif read hurry level 0x7 */
+ hurry = mmio_read_32(IMX_HDMI_CTL_BASE + TX_CONTROL0);
+ hurry |= 0x00077000;
+ mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry);
+ }
+
+ if (domain_id == MEDIAMIX) {
+ /* handle mediamix special */
+ mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RSTn_CSR, 0x1FFFFFF);
+ mmio_write_32(IMX_MEDIAMIX_CTL_BASE + CLK_EN_CSR, 0x1FFFFFF);
+ mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RST_DIV, 0x40030000);
+
+ /* set GPR to make lcdif read hurry level 0x7 */
+ hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL);
+ hurry |= 0xfc00;
+ mmio_write_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL, hurry);
+ /* set GPR to make isi write hurry level 0x7 */
+ hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL);
+ hurry |= 0x1ff00000;
+ mmio_write_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL, hurry);
+ }
+
+ /* set MIX NoC */
+ for (i = 0; i < ARRAY_SIZE(noc_setting); i++) {
+ if (noc_setting[i].domain_id == domain_id) {
+ udelay(50);
+ uint32_t offset = noc_setting[i].start;
+
+ while (offset <= noc_setting[i].end) {
+ mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy);
+ mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode);
+ mmio_write_32(IMX_NOC_BASE + offset + 0x18, noc_setting[i].socket_qos_en);
+ offset += 0x80;
+ }
+ }
+ }
+}
+
+static void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)
+{
+ struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];
+ unsigned int i;
+
+ if (domain_id == HSIOMIX) {
+ for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
+ hsiomix_clk[i].val = mmio_read_32(IMX_CCM_BASE + hsiomix_clk[i].offset);
+ mmio_setbits_32(IMX_CCM_BASE + hsiomix_clk[i].offset,
+ hsiomix_clk[i].type == CCM_ROOT_SLICE ? BIT(28) : 0x3);
+ }
+ }
+
+ if (on) {
+ if (pwr_domain->need_sync) {
+ pu_domain_status |= (1 << domain_id);
+ }
+
+ if (domain_id == HDMIMIX) {
+ /* assert the reset */
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0);
+ /* enable all th function clock */
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
+ }
+
+ /* clear the PGC bit */
+ mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
+
+ /* power up the domain */
+ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req);
+
+ /* wait for power request done */
+ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req)
+ ;
+
+ if (domain_id == HDMIMIX) {
+ /* wait for memory repair done for HDMIMIX */
+ while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8)))
+ ;
+ /* disable all the function clock */
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0);
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0);
+ /* deassert the reset */
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff);
+ /* enable all the clock again */
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF);
+ mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e);
+ }
+
+ if (domain_id == HSIOMIX) {
+ /* enable HSIOMIX clock */
+ mmio_write_32(IMX_HSIOMIX_CTL_BASE, 0x2);
+ }
+
+ /* handle the ADB400 sync */
+ if (pwr_domain->need_sync) {
+ /* clear adb power down request */
+ mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
+
+ /* wait for adb power request ack */
+ while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
+ ;
+ }
+
+ imx_noc_qos(domain_id);
+
+ /* AIPS5 config is lost when audiomix is off, so need to re-init it */
+ if (domain_id == AUDIOMIX) {
+ imx_aipstz_init(aipstz5);
+ }
+ } else {
+ if (pwr_domain->always_on) {
+ return;
+ }
+
+ if (pwr_domain->need_sync) {
+ pu_domain_status &= ~(1 << domain_id);
+ }
+
+ /* handle the ADB400 sync */
+ if (pwr_domain->need_sync) {
+ /* set adb power down request */
+ mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync);
+
+ /* wait for adb power request ack */
+ while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack))
+ ;
+ }
+
+ /* set the PGC bit */
+ mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1);
+
+ /*
+ * leave the G1, G2, H1 power domain on until VPUMIX power off,
+ * otherwise system will hang due to VPUMIX ACK
+ */
+ if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) {
+ return;
+ }
+
+ if (domain_id == VPUMIX) {
+ mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ |
+ VPU_G2_PWR_REQ | VPU_H1_PWR_REQ);
+
+ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ |
+ VPU_G2_PWR_REQ | VPU_H1_PWR_REQ))
+ ;
+ }
+
+ /* power down the domain */
+ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req);
+
+ /* wait for power request done */
+ while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req)
+ ;
+
+ if (domain_id == HDMIMIX) {
+ /* disable all the clocks of HDMIMIX */
+ mmio_write_32(IMX_HDMI_CTL_BASE + 0x40, 0x0);
+ mmio_write_32(IMX_HDMI_CTL_BASE + 0x50, 0x0);
+ }
+ }
+
+ if (domain_id == HSIOMIX) {
+ for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) {
+ mmio_write_32(IMX_CCM_BASE + hsiomix_clk[i].offset, hsiomix_clk[i].val);
+ }
+ }
+}
+
+void imx_gpc_init(void)
+{
+ uint32_t val;
+ unsigned int i;
+
+ /* mask all the wakeup irq by default */
+ for (i = 0; i < IMR_NUM; i++) {
+ mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
+ mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
+ mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
+ mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
+ mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
+ }
+
+ val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
+ /* use GIC wake_request to wakeup C0~C3 from LPM */
+ val |= CORE_WKUP_FROM_GIC;
+ /* clear the MASTER0 LPM handshake */
+ val &= ~MASTER0_LPM_HSK;
+ mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
+
+ /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
+ mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
+ MASTER2_MAPPING));
+
+ /* set all mix/PU in A53 domain */
+ mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0x3fffff);
+
+ /*
+ * Set the CORE & SCU power up timing:
+ * SW = 0x1, SW2ISO = 0x1;
+ * the CPU CORE and SCU power up timming counter
+ * is drived by 32K OSC, each domain's power up
+ * latency is (SW + SW2ISO) / 32768
+ */
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401);
+ mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
+ (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT));
+
+ /* set DUMMY PDN/PUP ACK by default for A53 domain */
+ mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
+ A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
+
+ /* clear DSM by default */
+ val = mmio_read_32(IMX_GPC_BASE + SLPCR);
+ val &= ~SLPCR_EN_DSM;
+ /* enable the fast wakeup wait/stop mode */
+ val |= SLPCR_A53_FASTWUP_WAIT_MODE;
+ val |= SLPCR_A53_FASTWUP_STOP_MODE;
+ /* clear the RBC */
+ val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
+ /* set the STBY_COUNT to 0x5, (128 * 30)us */
+ val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
+ val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
+ mmio_write_32(IMX_GPC_BASE + SLPCR, val);
+
+ /*
+ * USB PHY power up needs to make sure RESET bit in SRC is clear,
+ * otherwise, the PU power up bit in GPC will NOT self-cleared.
+ * only need to do it once.
+ */
+ mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
+ mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
+
+ /* enable all the power domain by default */
+ for (i = 0; i < 101; i++) {
+ mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3);
+ }
+
+ for (i = 0; i < 20; i++) {
+ imx_gpc_pm_domain_enable(i, true);
+ }
+}
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
new file mode 100644
index 0000000..22fbd5e
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <context.h>
+#include <drivers/arm/tzc380.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+
+#include <gpc.h>
+#include <imx_aipstz.h>
+#include <imx_uart.h>
+#include <imx_rdc.h>
+#include <imx8m_caam.h>
+#include <platform_def.h>
+#include <plat_imx8.h>
+
+static const mmap_region_t imx_mmap[] = {
+ GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
+ NOC_MAP, {0},
+};
+
+static const struct aipstz_cfg aipstz[] = {
+ {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
+static const struct imx_rdc_cfg rdc[] = {
+ /* Master domain assignment */
+ RDC_MDAn(0x1, DID1),
+
+ /* peripherals domain permission */
+
+ /* memory region */
+
+ /* Sentinel */
+ {0},
+};
+
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+/* get SPSR for BL33 entry */
+static uint32_t get_spsr_for_bl33_entry(void)
+{
+ unsigned long el_status;
+ unsigned long mode;
+ uint32_t spsr;
+
+ /* figure out what mode we enter the non-secure world */
+ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+ el_status &= ID_AA64PFR0_ELX_MASK;
+
+ mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+
+static void bl31_tzc380_setup(void)
+{
+ unsigned int val;
+
+ val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
+ if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
+ return;
+
+ tzc380_init(IMX_TZASC_BASE);
+
+ /*
+ * Need to substact offset 0x40000000 from CPU address when
+ * programming tzasc region for i.mx8mp.
+ */
+
+ /* Enable 1G-5G S/NS RW */
+ tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
+ TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
+}
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ static console_t console;
+ unsigned int i;
+
+ /* Enable CSU NS access permission */
+ for (i = 0; i < 64; i++) {
+ mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
+ }
+
+ imx_aipstz_init(aipstz);
+
+ imx_rdc_init(rdc);
+
+ imx8m_caam_init();
+
+ console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+ IMX_CONSOLE_BAUDRATE, &console);
+ /* This console is only used for boot stage */
+ console_set_scope(&console, CONSOLE_FLAG_BOOT);
+
+ /*
+ * tell BL3-1 where the non-secure software image is located
+ * and the entry state information.
+ */
+ bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
+ bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+#ifdef SPD_opteed
+ /* Populate entry point information for BL32 */
+ SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = 0;
+
+ /* Pass TEE base and size to bl33 */
+ bl33_image_ep_info.args.arg1 = BL32_BASE;
+ bl33_image_ep_info.args.arg2 = BL32_SIZE;
+#endif
+
+ bl31_tzc380_setup();
+}
+
+void bl31_plat_arch_setup(void)
+{
+ mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
+ MT_MEMORY | MT_RW | MT_SECURE);
+ mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
+ MT_MEMORY | MT_RO | MT_SECURE);
+#if USE_COHERENT_MEM
+ mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+ (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+ mmap_add(imx_mmap);
+
+ init_xlat_tables();
+
+ enable_mmu_el3(0);
+}
+
+void bl31_platform_setup(void)
+{
+ generic_delay_timer_init();
+
+ /* select the CKIL source to 32K OSC */
+ mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
+
+ plat_gic_driver_init();
+ plat_gic_init();
+
+ imx_gpc_init();
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
+{
+ if (type == NON_SECURE) {
+ return &bl33_image_ep_info;
+ }
+
+ if (type == SECURE) {
+ return &bl32_image_ep_info;
+ }
+
+ return NULL;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return COUNTER_FREQUENCY;
+}
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_psci.c b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
new file mode 100644
index 0000000..bc7b246
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+
+#include <gpc.h>
+#include <imx8m_psci.h>
+#include <plat_imx8.h>
+
+static const plat_psci_ops_t imx_plat_psci_ops = {
+ .pwr_domain_on = imx_pwr_domain_on,
+ .pwr_domain_on_finish = imx_pwr_domain_on_finish,
+ .pwr_domain_off = imx_pwr_domain_off,
+ .validate_ns_entrypoint = imx_validate_ns_entrypoint,
+ .validate_power_state = imx_validate_power_state,
+ .cpu_standby = imx_cpu_standby,
+ .pwr_domain_suspend = imx_domain_suspend,
+ .pwr_domain_suspend_finish = imx_domain_suspend_finish,
+ .pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
+ .get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
+ .system_reset = imx_system_reset,
+ .system_off = imx_system_off,
+};
+
+/* export the platform specific psci ops */
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ /* sec_entrypoint is used for warm reset */
+ imx_mailbox_init(sec_entrypoint);
+
+ *psci_ops = &imx_plat_psci_ops;
+
+ return 0;
+}
diff --git a/plat/imx/imx8m/imx8mp/include/gpc_reg.h b/plat/imx/imx8m/imx8mp/include/gpc_reg.h
new file mode 100644
index 0000000..12da6ac
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/include/gpc_reg.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPC_REG_H
+#define GPC_REG_H
+
+#define LPCR_A53_BSC 0x0
+#define LPCR_A53_BSC2 0x180
+#define LPCR_A53_AD 0x4
+#define LPCR_M4 0x8
+#define SLPCR 0x14
+#define MST_CPU_MAPPING 0x18
+#define MLPCR 0x20
+#define PGC_ACK_SEL_A53 0x24
+#define IMR1_CORE0_A53 0x30
+#define IMR1_CORE1_A53 0x44
+#define IMR1_CORE2_A53 0x194
+#define IMR1_CORE3_A53 0x1A8
+#define IMR1_CORE0_M4 0x58
+
+#define SLT0_CFG 0x200
+#define GPC_PU_PWRHSK 0x190
+#define PGC_CPU_0_1_MAPPING 0x1CC
+#define CPU_PGC_UP_TRG 0xD0
+#define PU_PGC_UP_TRG 0xD8
+#define CPU_PGC_DN_TRG 0xDC
+#define PU_PGC_DN_TRG 0xE4
+#define LPS_CPU1 0xEC
+
+#define A53_CORE0_PGC 0x800
+#define A53_PLAT_PGC 0x900
+#define PLAT_PGC_PCR 0x900
+#define NOC_PGC_PCR 0xa40
+#define PGC_SCU_TIMING 0x910
+
+#define MASK_DSM_TRIGGER_A53 BIT(31)
+#define IRQ_SRC_A53_WUP BIT(30)
+#define IRQ_SRC_A53_WUP_SHIFT 30
+#define IRQ_SRC_C1 BIT(29)
+#define IRQ_SRC_C0 BIT(28)
+#define IRQ_SRC_C3 BIT(23)
+#define IRQ_SRC_C2 BIT(22)
+#define CPU_CLOCK_ON_LPM BIT(14)
+#define A53_CLK_ON_LPM BIT(14)
+#define MASTER0_LPM_HSK BIT(6)
+#define MASTER1_LPM_HSK BIT(7)
+#define MASTER2_LPM_HSK BIT(8)
+
+#define L2PGE BIT(31)
+#define EN_L2_WFI_PDN BIT(5)
+#define EN_PLAT_PDN BIT(4)
+
+#define SLPCR_EN_DSM BIT(31)
+#define SLPCR_RBC_EN BIT(30)
+#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
+#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
+#define SLPCR_VSTBY BIT(2)
+#define SLPCR_SBYOS BIT(1)
+#define SLPCR_BYPASS_PMIC_READY BIT(0)
+#define SLPCR_RBC_COUNT_SHIFT 24
+#define SLPCR_STBY_COUNT_SHFT 3
+
+#define A53_DUMMY_PDN_ACK BIT(30)
+#define A53_DUMMY_PUP_ACK BIT(31)
+#define A53_PLAT_PDN_ACK BIT(8)
+#define A53_PLAT_PUP_ACK BIT(9)
+
+#define NOC_PDN_SLT_CTRL BIT(12)
+#define NOC_PUP_SLT_CTRL BIT(13)
+#define NOC_PGC_PDN_ACK BIT(12)
+#define NOC_PGC_PUP_ACK BIT(13)
+
+#define PLAT_PUP_SLT_CTRL BIT(9)
+#define PLAT_PDN_SLT_CTRL BIT(8)
+
+#define SLT_PLAT_PDN BIT(8)
+#define SLT_PLAT_PUP BIT(9)
+
+#define MASTER1_MAPPING BIT(1)
+#define MASTER2_MAPPING BIT(2)
+
+#define TMR_TCD2_SHIFT 0
+#define TMC_TMR_SHIFT 10
+#define TRC1_TMC_SHIFT 20
+
+#define MIPI_PHY1_PWR_REQ BIT(0)
+#define PCIE_PHY_PWR_REQ BIT(1)
+#define USB1_PHY_PWR_REQ BIT(2)
+#define USB2_PHY_PWR_REQ BIT(3)
+#define MLMIX_PWR_REQ BIT(4)
+#define AUDIOMIX_PWR_REQ BIT(5)
+#define GPU2D_PWR_REQ BIT(6)
+#define GPUMIX_PWR_REQ BIT(7)
+#define VPUMIX_PWR_REQ BIT(8)
+#define GPU3D_PWR_REQ BIT(9)
+#define MEDIAMIX_PWR_REQ BIT(10)
+#define VPU_G1_PWR_REQ BIT(11)
+#define VPU_G2_PWR_REQ BIT(12)
+#define VPU_H1_PWR_REQ BIT(13)
+#define HDMIMIX_PWR_REQ BIT(14)
+#define HDMI_PHY_PWR_REQ BIT(15)
+#define MIPI_PHY2_PWR_REQ BIT(16)
+#define HSIOMIX_PWR_REQ BIT(17)
+#define MEDIAMIX_ISPDWP_PWR_REQ BIT(18)
+#define DDRMIX_PWR_REQ BIT(19)
+
+#define AUDIOMIX_ADB400_SYNC (BIT(4) | BIT(15))
+#define MLMIX_ADB400_SYNC (BIT(7) | BIT(8))
+#define GPUMIX_ADB400_SYNC BIT(9)
+#define VPUMIX_ADB400_SYNC BIT(10)
+#define DDRMIX_ADB400_SYNC BIT(11)
+#define HSIOMIX_ADB400_SYNC BIT(12)
+#define HDMIMIX_ADB400_SYNC BIT(13)
+#define MEDIAMIX_ADB400_SYNC BIT(14)
+
+#define AUDIOMIX_ADB400_ACK (BIT(20) | BIT(31))
+#define MLMIX_ADB400_ACK (BIT(23) | BIT(24))
+#define GPUMIX_ADB400_ACK BIT(25)
+#define VPUMIX_ADB400_ACK BIT(26)
+#define DDRMIX_ADB400_ACK BIT(27)
+#define HSIOMIX_ADB400_ACK BIT(28)
+#define HDMIMIX_ADB400_ACK BIT(29)
+#define MEDIAMIX_ADB400_ACK BIT(30)
+
+#define MIPI_PHY1_PGC 0xb00
+#define PCIE_PHY_PGC 0xb40
+#define USB1_PHY_PGC 0xb80
+#define USB2_PHY_PGC 0xbc0
+#define MLMIX_PGC 0xc00
+#define AUDIOMIX_PGC 0xc40
+#define GPU2D_PGC 0xc80
+#define GPUMIX_PGC 0xcc0
+#define VPUMIX_PGC 0xd00
+#define GPU3D_PGC 0xd40
+#define MEDIAMIX_PGC 0xd80
+#define VPU_G1_PGC 0xdc0
+#define VPU_G2_PGC 0xe00
+#define VPU_H1_PGC 0xe40
+#define HDMIMIX_PGC 0xe80
+#define HDMI_PHY_PGC 0xec0
+#define MIPI_PHY2_PGC 0xf00
+#define HSIOMIX_PGC 0xf40
+#define MEDIAMIX_ISPDWP_PGC 0xf80
+#define DDRMIX_PGC 0xfc0
+
+#endif /* GPC_REG_H */
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
new file mode 100644
index 0000000..644adc7
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define PLATFORM_STACK_SIZE 0xB00
+#define CACHE_WRITEBACK_GRANULE 64
+
+#define PLAT_PRIMARY_CPU U(0x0)
+#define PLATFORM_MAX_CPU_PER_CLUSTER U(4)
+#define PLATFORM_CLUSTER_COUNT U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
+#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
+
+#define IMX_PWR_LVL0 MPIDR_AFFLVL0
+#define IMX_PWR_LVL1 MPIDR_AFFLVL1
+#define IMX_PWR_LVL2 MPIDR_AFFLVL2
+
+#define PWR_DOMAIN_AT_MAX_LVL U(1)
+#define PLAT_MAX_PWR_LVL U(2)
+#define PLAT_MAX_OFF_STATE U(4)
+#define PLAT_MAX_RET_STATE U(2)
+
+#define PLAT_WAIT_RET_STATE U(1)
+#define PLAT_STOP_OFF_STATE U(3)
+
+#define BL31_BASE U(0x960000)
+#define BL31_LIMIT U(0x980000)
+
+/* non-secure uboot base */
+#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+
+/* GICv3 base address */
+#define PLAT_GICD_BASE U(0x38800000)
+#define PLAT_GICR_BASE U(0x38880000)
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
+
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 16
+
+#define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */
+
+#define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */
+#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
+#define PLAT_CRASH_UART_CLK_IN_HZ 24000000
+#define IMX_CONSOLE_BAUDRATE 115200
+
+#define IMX_AIPSTZ1 U(0x301f0000)
+#define IMX_AIPSTZ2 U(0x305f0000)
+#define IMX_AIPSTZ3 U(0x309f0000)
+#define IMX_AIPSTZ4 U(0x32df0000)
+#define IMX_AIPSTZ5 U(0x30df0000)
+
+#define IMX_AIPS_BASE U(0x30000000)
+#define IMX_AIPS_SIZE U(0x3000000)
+#define IMX_GPV_BASE U(0x32000000)
+#define IMX_GPV_SIZE U(0x800000)
+#define IMX_AIPS1_BASE U(0x30200000)
+#define IMX_AIPS4_BASE U(0x32c00000)
+#define IMX_ANAMIX_BASE U(0x30360000)
+#define IMX_CCM_BASE U(0x30380000)
+#define IMX_SRC_BASE U(0x30390000)
+#define IMX_GPC_BASE U(0x303a0000)
+#define IMX_RDC_BASE U(0x303d0000)
+#define IMX_CSU_BASE U(0x303e0000)
+#define IMX_WDOG_BASE U(0x30280000)
+#define IMX_SNVS_BASE U(0x30370000)
+#define IMX_NOC_BASE U(0x32700000)
+#define IMX_NOC_SIZE U(0x100000)
+#define IMX_TZASC_BASE U(0x32F80000)
+#define IMX_IOMUX_GPR_BASE U(0x30340000)
+#define IMX_CAAM_BASE U(0x30900000)
+#define IMX_DDRC_BASE U(0x3d400000)
+#define IMX_DDRPHY_BASE U(0x3c000000)
+#define IMX_DDR_IPS_BASE U(0x3d000000)
+#define IMX_DDR_IPS_SIZE U(0x1800000)
+#define IMX_ROM_BASE U(0x0)
+
+#define IMX_GIC_BASE PLAT_GICD_BASE
+#define IMX_GIC_SIZE U(0x200000)
+
+#define IMX_HSIOMIX_CTL_BASE U(0x32f10000)
+#define IMX_HDMI_CTL_BASE U(0x32fc0000)
+#define RTX_RESET_CTL0 U(0x20)
+#define RTX_CLK_CTL0 U(0x40)
+#define RTX_CLK_CTL1 U(0x50)
+#define TX_CONTROL0 U(0x200)
+#define TX_CONTROL1 U(0x220)
+
+#define IMX_MEDIAMIX_CTL_BASE U(0x32ec0000)
+#define RSTn_CSR U(0x0)
+#define CLK_EN_CSR U(0x4)
+#define RST_DIV U(0x8)
+#define LCDIF_ARCACHE_CTRL U(0x4c)
+#define ISI_CACHE_CTRL U(0x50)
+
+#define WDOG_WSR U(0x2)
+#define WDOG_WCR_WDZST BIT(0)
+#define WDOG_WCR_WDBG BIT(1)
+#define WDOG_WCR_WDE BIT(2)
+#define WDOG_WCR_WDT BIT(3)
+#define WDOG_WCR_SRS BIT(4)
+#define WDOG_WCR_WDA BIT(5)
+#define WDOG_WCR_SRE BIT(6)
+#define WDOG_WCR_WDW BIT(7)
+
+#define SRC_A53RCR0 U(0x4)
+#define SRC_A53RCR1 U(0x8)
+#define SRC_OTG1PHY_SCR U(0x20)
+#define SRC_OTG2PHY_SCR U(0x24)
+#define SRC_GPR1_OFFSET U(0x74)
+
+#define SNVS_LPCR U(0x38)
+#define SNVS_LPCR_SRTC_ENV BIT(0)
+#define SNVS_LPCR_DP_EN BIT(5)
+#define SNVS_LPCR_TOP BIT(6)
+
+#define IOMUXC_GPR10 U(0x28)
+#define GPR_TZASC_EN BIT(0)
+#define GPR_TZASC_EN_LOCK BIT(16)
+
+#define ANAMIX_MISC_CTL U(0x124)
+#define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50)
+
+#define MAX_CSU_NUM U(64)
+
+#define OCRAM_S_BASE U(0x00180000)
+#define OCRAM_S_SIZE U(0x8000)
+#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
+#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE
+
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+#define IMX_WDOG_B_RESET
+
+#define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW)
+#define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */
+#define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */
+#define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */
+#define NOC_MAP MAP_REGION_FLAT(IMX_NOC_BASE, IMX_NOC_SIZE, MT_DEVICE | MT_RW) /* NOC QoS */
+
+#endif /* platform_def.h */
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
new file mode 100644
index 0000000..1d11e3d
--- /dev/null
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -0,0 +1,56 @@
+#
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES := -Iplat/imx/common/include \
+ -Iplat/imx/imx8m/include \
+ -Iplat/imx/imx8m/imx8mp/include
+# Translation tables library
+include lib/xlat_tables_v2/xlat_tables.mk
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+IMX_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/common/plat_psci_common.c \
+ plat/imx/common/plat_imx8_gic.c
+
+BL31_SOURCES += plat/imx/common/imx8_helpers.S \
+ plat/imx/imx8m/gpc_common.c \
+ plat/imx/imx8m/imx_aipstz.c \
+ plat/imx/imx8m/imx_rdc.c \
+ plat/imx/imx8m/imx8m_caam.c \
+ plat/imx/imx8m/imx8m_psci_common.c \
+ plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c \
+ plat/imx/imx8m/imx8mp/imx8mp_psci.c \
+ plat/imx/imx8m/imx8mp/gpc.c \
+ plat/imx/common/imx8_topology.c \
+ plat/imx/common/imx_sip_handler.c \
+ plat/imx/common/imx_sip_svc.c \
+ plat/imx/common/imx_uart_console.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ drivers/arm/tzc/tzc380.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ ${IMX_GIC_SOURCES} \
+ ${XLAT_TABLES_LIB_SRCS}
+
+USE_COHERENT_MEM := 1
+RESET_TO_BL31 := 1
+A53_DISABLE_NON_TEMPORAL_HINT := 0
+
+ERRATA_A53_835769 := 1
+ERRATA_A53_843419 := 1
+ERRATA_A53_855873 := 1
+
+BL32_BASE ?= 0x56000000
+$(eval $(call add_define,BL32_BASE))
+
+BL32_SIZE ?= 0x2000000
+$(eval $(call add_define,BL32_SIZE))
+
+IMX_BOOT_UART_BASE ?= 0x30890000
+$(eval $(call add_define,IMX_BOOT_UART_BASE))
diff --git a/plat/imx/imx8m/imx8mq/include/gpc_reg.h b/plat/imx/imx8m/imx8mq/include/gpc_reg.h
new file mode 100644
index 0000000..9f472d6
--- /dev/null
+++ b/plat/imx/imx8m/imx8mq/include/gpc_reg.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GPC_REG_H
+#define GPC_REG_H
+
+#define LPCR_A53_BSC 0x0
+#define LPCR_A53_BSC2 0x108
+#define LPCR_A53_AD 0x4
+#define LPCR_M4 0x8
+#define SLPCR 0x14
+#define MST_CPU_MAPPING 0x18
+#define MLPCR 0x20
+#define PGC_ACK_SEL_A53 0x24
+#define IMR1_CORE0_A53 0x30
+#define IMR1_CORE1_A53 0x40
+#define IMR1_CORE2_A53 0x1C0
+#define IMR1_CORE3_A53 0x1D0
+#define IMR1_CORE0_M4 0x50
+#define SLT0_CFG 0xB0
+#define GPC_PU_PWRHSK 0x1FC
+#define PGC_CPU_0_1_MAPPING 0xEC
+#define CPU_PGC_UP_TRG 0xF0
+#define PU_PGC_UP_TRG 0xF8
+#define CPU_PGC_DN_TRG 0xFC
+#define PU_PGC_DN_TRG 0x104
+#define LPS_CPU1 0x114
+#define A53_CORE0_PGC 0x800
+#define A53_PLAT_PGC 0x900
+#define PLAT_PGC_PCR 0x900
+#define NOC_PGC_PCR 0xa40
+#define PGC_SCU_TIMING 0x910
+
+#define MASK_DSM_TRIGGER_A53 BIT(31)
+#define IRQ_SRC_A53_WUP BIT(30)
+#define IRQ_SRC_A53_WUP_SHIFT 30
+#define IRQ_SRC_C1 BIT(29)
+#define IRQ_SRC_C0 BIT(28)
+#define IRQ_SRC_C3 BIT(23)
+#define IRQ_SRC_C2 BIT(22)
+#define CPU_CLOCK_ON_LPM BIT(14)
+#define A53_CLK_ON_LPM BIT(14)
+#define MASTER0_LPM_HSK BIT(6)
+#define MASTER1_LPM_HSK BIT(7)
+#define MASTER2_LPM_HSK BIT(8)
+
+#define L2PGE BIT(31)
+#define EN_L2_WFI_PDN BIT(5)
+#define EN_PLAT_PDN BIT(4)
+
+#define SLPCR_EN_DSM BIT(31)
+#define SLPCR_RBC_EN BIT(30)
+#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
+#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
+#define SLPCR_VSTBY BIT(2)
+#define SLPCR_SBYOS BIT(1)
+#define SLPCR_BYPASS_PMIC_READY BIT(0)
+#define SLPCR_RBC_COUNT_SHIFT 24
+#define SLPCR_STBY_COUNT_SHFT 3
+
+#define A53_DUMMY_PDN_ACK BIT(15)
+#define A53_DUMMY_PUP_ACK BIT(31)
+#define A53_PLAT_PDN_ACK BIT(2)
+#define A53_PLAT_PUP_ACK BIT(18)
+#define NOC_PDN_SLT_CTRL BIT(10)
+#define NOC_PUP_SLT_CTRL BIT(11)
+#define NOC_PGC_PDN_ACK BIT(3)
+#define NOC_PGC_PUP_ACK BIT(19)
+
+#define DDRMIX_PWR_REQ BIT(5)
+#define DDRMIX_ADB400_SYNC BIT(1)
+#define DDRMIX_ADB400_ACK BIT(18)
+#define DDRMIX_PGC 0xd40
+
+#define PLAT_PUP_SLT_CTRL BIT(9)
+#define PLAT_PDN_SLT_CTRL BIT(8)
+
+#define SLT_PLAT_PDN BIT(8)
+#define SLT_PLAT_PUP BIT(9)
+
+#define MASTER1_MAPPING BIT(1)
+#define MASTER2_MAPPING BIT(2)
+
+#endif /* GPC_REG_H */
diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h
index 6033b0d..89a0b9d 100644
--- a/plat/imx/imx8m/include/gpc.h
+++ b/plat/imx/imx8m/include/gpc.h
@@ -7,74 +7,7 @@
#ifndef IMX8M_GPC_H
#define IMX8M_GPC_H
-#define LPCR_A53_BSC 0x0
-#define LPCR_A53_BSC2 0x108
-#define LPCR_A53_AD 0x4
-#define LPCR_M4 0x8
-#define SLPCR 0x14
-#define MST_CPU_MAPPING 0x18
-#define MLPCR 0x20
-#define PGC_ACK_SEL_A53 0x24
-#define IMR1_CORE0_A53 0x30
-#define IMR1_CORE1_A53 0x40
-#define IMR1_CORE2_A53 0x1C0
-#define IMR1_CORE3_A53 0x1D0
-#define IMR1_CORE0_M4 0x50
-#define SLT0_CFG 0xB0
-#define GPC_PU_PWRHSK 0x1FC
-#define PGC_CPU_0_1_MAPPING 0xEC
-#define CPU_PGC_UP_TRG 0xF0
-#define PU_PGC_UP_TRG 0xF8
-#define CPU_PGC_DN_TRG 0xFC
-#define PU_PGC_DN_TRG 0x104
-#define A53_CORE0_PGC 0x800
-#define A53_PLAT_PGC 0x900
-#define PLAT_PGC_PCR 0x900
-#define PGC_SCU_TIMING 0x910
-
-#define MASK_DSM_TRIGGER_A53 BIT(31)
-#define IRQ_SRC_A53_WUP BIT(30)
-#define IRQ_SRC_A53_WUP_SHIFT 30
-#define IRQ_SRC_C1 BIT(29)
-#define IRQ_SRC_C0 BIT(28)
-#define IRQ_SRC_C3 BIT(23)
-#define IRQ_SRC_C2 BIT(22)
-#define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3)
-#define CPU_CLOCK_ON_LPM BIT(14)
-#define A53_CLK_ON_LPM BIT(14)
-#define MASTER0_LPM_HSK BIT(6)
-
-#define L2PGE BIT(31)
-#define EN_L2_WFI_PDN BIT(5)
-#define EN_PLAT_PDN BIT(4)
-
-#define SLPCR_EN_DSM BIT(31)
-#define SLPCR_RBC_EN BIT(30)
-#define SLPCR_A53_FASTWUP_STOP_MODE BIT(17)
-#define SLPCR_A53_FASTWUP_WAIT_MODE BIT(16)
-#define SLPCR_VSTBY BIT(2)
-#define SLPCR_SBYOS BIT(1)
-#define SLPCR_BYPASS_PMIC_READY BIT(0)
-#define SLPCR_RBC_COUNT_SHIFT 24
-#define SLPCR_STBY_COUNT_SHFT 3
-
-#define A53_DUMMY_PDN_ACK BIT(15)
-#define A53_DUMMY_PUP_ACK BIT(31)
-#define A53_PLAT_PDN_ACK BIT(2)
-#define A53_PLAT_PUP_ACK BIT(18)
-
-#define PLAT_PUP_SLT_CTRL BIT(9)
-#define PLAT_PDN_SLT_CTRL BIT(8)
-
-#define SLT_PLAT_PDN BIT(8)
-#define SLT_PLAT_PUP BIT(9)
-
-#define MASTER1_MAPPING BIT(1)
-#define MASTER2_MAPPING BIT(2)
-
-#define TMR_TCD2_SHIFT 0
-#define TMC_TMR_SHIFT 10
-#define TRC1_TMC_SHIFT 20
+#include <gpc_reg.h>
/* helper macro */
#define A53_LPM_MASK U(0xF)
@@ -83,7 +16,7 @@
#define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP)
#define DSM_MODE_MASK BIT(31)
-
+#define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3)
#define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2))
#define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40)
#define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16))
@@ -95,6 +28,33 @@
#define IRQ_IMR_NUM 4
#define IMR_MASK_ALL 0xffffffff
+#define IMX_PD_DOMAIN(name, on) \
+ { \
+ .pwr_req = name##_PWR_REQ, \
+ .pgc_offset = name##_PGC, \
+ .need_sync = false, \
+ .always_on = true, \
+ }
+
+#define IMX_MIX_DOMAIN(name, on) \
+ { \
+ .pwr_req = name##_PWR_REQ, \
+ .pgc_offset = name##_PGC, \
+ .adb400_sync = name##_ADB400_SYNC, \
+ .adb400_ack = name##_ADB400_ACK, \
+ .need_sync = true, \
+ .always_on = true, \
+ }
+
+struct imx_pwr_domain {
+ uint32_t pwr_req;
+ uint32_t adb400_sync;
+ uint32_t adb400_ack;
+ uint32_t pgc_offset;
+ bool need_sync;
+ bool always_on;
+};
+
/* function declare */
void imx_gpc_init(void);
void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint);
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index 0a49d81..cfacd1f 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -17,6 +17,7 @@
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
#include <libfdt.h>
#include <drivers/arm/gicv2.h>
@@ -200,13 +201,6 @@
enable_mmu_el3(0);
}
-static uint32_t dtb_size(const void *dtb)
-{
- const uint32_t *dtb_header = dtb;
-
- return fdt32_to_cpu(dtb_header[1]);
-}
-
static void rpi4_prepare_dtb(void)
{
void *dtb = (void *)rpi4_get_dtb_address();
@@ -250,7 +244,7 @@
if (ret < 0)
ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
- clean_dcache_range((uintptr_t)dtb, dtb_size(dtb));
+ clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
INFO("Changed device tree to advertise PSCI.\n");
}
diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c
index 679f14d..4524610 100644
--- a/plat/socionext/uniphier/uniphier_bl2_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl2_setup.c
@@ -21,8 +21,8 @@
#include "uniphier.h"
-#define UNIPHIER_IMAGE_BUF_OFFSET 0x04300000UL
-#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL
+#define UNIPHIER_IMAGE_BUF_OFFSET 0x03800000UL
+#define UNIPHIER_IMAGE_BUF_SIZE 0x00800000UL
static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
diff --git a/plat/socionext/uniphier/uniphier_image_desc.c b/plat/socionext/uniphier/uniphier_image_desc.c
index 8c232ba..dd62d1e 100644
--- a/plat/socionext/uniphier/uniphier_image_desc.c
+++ b/plat/socionext/uniphier/uniphier_image_desc.c
@@ -14,9 +14,9 @@
#include "uniphier.h"
#define UNIPHIER_BL33_OFFSET 0x04000000UL
-#define UNIPHIER_BL33_MAX_SIZE 0x00100000UL
+#define UNIPHIER_BL33_MAX_SIZE 0x00800000UL
-#define UNIPHIER_SCP_OFFSET 0x04100000UL
+#define UNIPHIER_SCP_OFFSET 0x04800000UL
#define UNIPHIER_SCP_MAX_SIZE 0x00020000UL
static struct bl_mem_params_node uniphier_image_descs[] = {
diff --git a/plat/socionext/uniphier/uniphier_io_storage.c b/plat/socionext/uniphier/uniphier_io_storage.c
index 77d1eaf..92e15b0 100644
--- a/plat/socionext/uniphier/uniphier_io_storage.c
+++ b/plat/socionext/uniphier/uniphier_io_storage.c
@@ -25,8 +25,8 @@
#define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL
-#define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL
-#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL
+#define UNIPHIER_BLOCK_BUF_OFFSET 0x03000000UL
+#define UNIPHIER_BLOCK_BUF_SIZE 0x00800000UL
static const io_dev_connector_t *uniphier_fip_dev_con;
static uintptr_t uniphier_fip_dev_handle;
diff --git a/plat/st/common/include/stm32mp_shared_resources.h b/plat/st/common/include/stm32mp_shared_resources.h
index b148666..13f4b13 100644
--- a/plat/st/common/include/stm32mp_shared_resources.h
+++ b/plat/st/common/include/stm32mp_shared_resources.h
@@ -8,6 +8,10 @@
#define STM32MP_SHARED_RESOURCES_H
#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef STM32MP_SHARED_RESOURCES
+enum stm32mp_shres;
/* Return true if @clock_id is shared by secure and non-secure worlds */
bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
@@ -15,7 +19,40 @@
/* Return true if and only if @reset_id relates to a non-secure peripheral */
bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
+/* Register a shared resource assigned to the secure world */
+void stm32mp_register_secure_periph(enum stm32mp_shres id);
+
+/* Register a shared resource assigned to the non-secure world */
+void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
+
+/* Register a peripheral as secure or non-secure based on IO base address */
+void stm32mp_register_secure_periph_iomem(uintptr_t base);
+void stm32mp_register_non_secure_periph_iomem(uintptr_t base);
+
+/* Register a GPIO as secure or non-secure based on its bank and pin numbers */
+void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin);
+void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin);
+
/* Consolidate peripheral states and lock against new peripheral registering */
void stm32mp_lock_periph_registering(void);
+#else
+static inline void stm32mp_register_secure_periph_iomem(uintptr_t base __unused)
+{
+}
+static inline
+void stm32mp_register_non_secure_periph_iomem(uintptr_t base __unused)
+{
+}
+
+static inline void stm32mp_register_secure_gpio(unsigned int bank __unused,
+ unsigned int pin __unused)
+{
+}
+
+static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused,
+ unsigned int pin __unused)
+{
+}
+#endif /* STM32MP_SHARED_RESOURCES */
#endif /* STM32MP_SHARED_RESOURCES_H */
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index ef82d5e..bce5994 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -494,14 +494,16 @@
#define IWDG2_BASE U(0x5A002000)
/*******************************************************************************
- * STM32MP1 I2C4
+ * Miscellaneous STM32MP1 peripherals base address
******************************************************************************/
-#define I2C4_BASE U(0x5C002000)
-
-/*******************************************************************************
- * STM32MP1 DBGMCU
- ******************************************************************************/
+#define CRYP1_BASE U(0x54001000)
#define DBGMCU_BASE U(0x50081000)
+#define HASH1_BASE U(0x54002000)
+#define I2C4_BASE U(0x5C002000)
+#define I2C6_BASE U(0x5c009000)
+#define RNG1_BASE U(0x54003000)
+#define RTC_BASE U(0x5c004000)
+#define SPI6_BASE U(0x5c001000)
/*******************************************************************************
* Device Tree defines
diff --git a/plat/st/stm32mp1/stm32mp1_shared_resources.c b/plat/st/stm32mp1/stm32mp1_shared_resources.c
index 268aa52..208e34a 100644
--- a/plat/st/stm32mp1/stm32mp1_shared_resources.c
+++ b/plat/st/stm32mp1/stm32mp1_shared_resources.c
@@ -44,6 +44,49 @@
/* Force uint8_t array for array of enum shres_state for size considerations */
static uint8_t shres_state[STM32MP1_SHRES_COUNT];
+static const char *shres2str_id_tbl[STM32MP1_SHRES_COUNT] __unused = {
+ [STM32MP1_SHRES_GPIOZ(0)] = "GPIOZ0",
+ [STM32MP1_SHRES_GPIOZ(1)] = "GPIOZ1",
+ [STM32MP1_SHRES_GPIOZ(2)] = "GPIOZ2",
+ [STM32MP1_SHRES_GPIOZ(3)] = "GPIOZ3",
+ [STM32MP1_SHRES_GPIOZ(4)] = "GPIOZ4",
+ [STM32MP1_SHRES_GPIOZ(5)] = "GPIOZ5",
+ [STM32MP1_SHRES_GPIOZ(6)] = "GPIOZ6",
+ [STM32MP1_SHRES_GPIOZ(7)] = "GPIOZ7",
+ [STM32MP1_SHRES_IWDG1] = "IWDG1",
+ [STM32MP1_SHRES_USART1] = "USART1",
+ [STM32MP1_SHRES_SPI6] = "SPI6",
+ [STM32MP1_SHRES_I2C4] = "I2C4",
+ [STM32MP1_SHRES_RNG1] = "RNG1",
+ [STM32MP1_SHRES_HASH1] = "HASH1",
+ [STM32MP1_SHRES_CRYP1] = "CRYP1",
+ [STM32MP1_SHRES_I2C6] = "I2C6",
+ [STM32MP1_SHRES_RTC] = "RTC",
+ [STM32MP1_SHRES_MCU] = "MCU",
+ [STM32MP1_SHRES_MDMA] = "MDMA",
+ [STM32MP1_SHRES_PLL3] = "PLL3",
+};
+
+static const char __unused *shres2str_id(enum stm32mp_shres id)
+{
+ assert(id < ARRAY_SIZE(shres2str_id_tbl));
+
+ return shres2str_id_tbl[id];
+}
+
+static const char __unused *shres2str_state_tbl[] = {
+ [SHRES_UNREGISTERED] = "unregistered",
+ [SHRES_NON_SECURE] = "non-secure",
+ [SHRES_SECURE] = "secure",
+};
+
+static const char __unused *shres2str_state(unsigned int state)
+{
+ assert(state < ARRAY_SIZE(shres2str_state_tbl));
+
+ return shres2str_state_tbl[state];
+}
+
/* Get resource state: these accesses lock the registering support */
static void lock_registering(void)
{
@@ -92,16 +135,344 @@
return get_gpio_nbpin(GPIO_BANK_Z);
}
-/* Currently allow full access by non-secure to platform clock services */
-bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
+static void register_periph(enum stm32mp_shres id, unsigned int state)
{
- return true;
+ assert((id < STM32MP1_SHRES_COUNT) &&
+ ((state == SHRES_SECURE) || (state == SHRES_NON_SECURE)));
+
+ if (registering_locked) {
+ if (shres_state[id] == state) {
+ return;
+ }
+ panic();
+ }
+
+ if ((shres_state[id] != SHRES_UNREGISTERED) &&
+ (shres_state[id] != state)) {
+ VERBOSE("Cannot change %s from %s to %s\n",
+ shres2str_id(id),
+ shres2str_state(shres_state[id]),
+ shres2str_state(state));
+ panic();
+ }
+
+ if (shres_state[id] == SHRES_UNREGISTERED) {
+ VERBOSE("Register %s as %s\n",
+ shres2str_id(id), shres2str_state(state));
+ }
+
+ if ((id >= STM32MP1_SHRES_GPIOZ(0)) &&
+ (id <= STM32MP1_SHRES_GPIOZ(7)) &&
+ ((id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin())) {
+ ERROR("Invalid GPIO pin %u, %u pin(s) available\n",
+ id - STM32MP1_SHRES_GPIOZ(0), get_gpioz_nbpin());
+ panic();
+ }
+
+ shres_state[id] = (uint8_t)state;
+
+ /* Explore clock tree to lock dependencies */
+ if (state == SHRES_SECURE) {
+ enum stm32mp_shres clock_res_id;
+
+ switch (id) {
+ case STM32MP1_SHRES_GPIOZ(0):
+ case STM32MP1_SHRES_GPIOZ(1):
+ case STM32MP1_SHRES_GPIOZ(2):
+ case STM32MP1_SHRES_GPIOZ(3):
+ case STM32MP1_SHRES_GPIOZ(4):
+ case STM32MP1_SHRES_GPIOZ(5):
+ case STM32MP1_SHRES_GPIOZ(6):
+ case STM32MP1_SHRES_GPIOZ(7):
+ clock_res_id = GPIOZ;
+ break;
+ case STM32MP1_SHRES_IWDG1:
+ clock_res_id = IWDG1;
+ break;
+ case STM32MP1_SHRES_USART1:
+ clock_res_id = USART1_K;
+ break;
+ case STM32MP1_SHRES_SPI6:
+ clock_res_id = SPI6_K;
+ break;
+ case STM32MP1_SHRES_I2C4:
+ clock_res_id = I2C4_K;
+ break;
+ case STM32MP1_SHRES_RNG1:
+ clock_res_id = RNG1_K;
+ break;
+ case STM32MP1_SHRES_HASH1:
+ clock_res_id = HASH1;
+ break;
+ case STM32MP1_SHRES_CRYP1:
+ clock_res_id = CRYP1;
+ break;
+ case STM32MP1_SHRES_I2C6:
+ clock_res_id = I2C6_K;
+ break;
+ case STM32MP1_SHRES_RTC:
+ clock_res_id = RTC;
+ break;
+ default:
+ /* No clock resource dependency */
+ return;
+ }
+
+ stm32mp1_register_clock_parents_secure(clock_res_id);
+ }
}
-/* Currently allow full access by non-secure to platform reset services */
+/* Register resource by ID */
+void stm32mp_register_secure_periph(enum stm32mp_shres id)
+{
+ register_periph(id, SHRES_SECURE);
+}
+
+void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
+{
+ register_periph(id, SHRES_NON_SECURE);
+}
+
+static void register_periph_iomem(uintptr_t base, unsigned int state)
+{
+ enum stm32mp_shres id;
+
+ switch (base) {
+ case CRYP1_BASE:
+ id = STM32MP1_SHRES_CRYP1;
+ break;
+ case HASH1_BASE:
+ id = STM32MP1_SHRES_HASH1;
+ break;
+ case I2C4_BASE:
+ id = STM32MP1_SHRES_I2C4;
+ break;
+ case I2C6_BASE:
+ id = STM32MP1_SHRES_I2C6;
+ break;
+ case IWDG1_BASE:
+ id = STM32MP1_SHRES_IWDG1;
+ break;
+ case RNG1_BASE:
+ id = STM32MP1_SHRES_RNG1;
+ break;
+ case RTC_BASE:
+ id = STM32MP1_SHRES_RTC;
+ break;
+ case SPI6_BASE:
+ id = STM32MP1_SHRES_SPI6;
+ break;
+ case USART1_BASE:
+ id = STM32MP1_SHRES_USART1;
+ break;
+
+ case GPIOA_BASE:
+ case GPIOB_BASE:
+ case GPIOC_BASE:
+ case GPIOD_BASE:
+ case GPIOE_BASE:
+ case GPIOF_BASE:
+ case GPIOG_BASE:
+ case GPIOH_BASE:
+ case GPIOI_BASE:
+ case GPIOJ_BASE:
+ case GPIOK_BASE:
+ case USART2_BASE:
+ case USART3_BASE:
+ case UART4_BASE:
+ case UART5_BASE:
+ case USART6_BASE:
+ case UART7_BASE:
+ case UART8_BASE:
+ case IWDG2_BASE:
+ /* Allow drivers to register some non-secure resources */
+ VERBOSE("IO for non-secure resource 0x%x\n",
+ (unsigned int)base);
+ if (state != SHRES_NON_SECURE) {
+ panic();
+ }
+
+ return;
+
+ default:
+ panic();
+ }
+
+ register_periph(id, state);
+}
+
+void stm32mp_register_secure_periph_iomem(uintptr_t base)
+{
+ register_periph_iomem(base, SHRES_SECURE);
+}
+
+void stm32mp_register_non_secure_periph_iomem(uintptr_t base)
+{
+ register_periph_iomem(base, SHRES_NON_SECURE);
+}
+
+void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin)
+{
+ switch (bank) {
+ case GPIO_BANK_Z:
+ register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_SECURE);
+ break;
+ default:
+ ERROR("GPIO bank %u cannot be secured\n", bank);
+ panic();
+ }
+}
+
+void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin)
+{
+ switch (bank) {
+ case GPIO_BANK_Z:
+ register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_NON_SECURE);
+ break;
+ default:
+ break;
+ }
+}
+
+static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
+{
+ unsigned int non_secure = 0U;
+ unsigned int i;
+
+ lock_registering();
+
+ if (bank != GPIO_BANK_Z) {
+ return true;
+ }
+
+ for (i = 0U; i < get_gpioz_nbpin(); i++) {
+ if (periph_is_non_secure(STM32MP1_SHRES_GPIOZ(i))) {
+ non_secure++;
+ }
+ }
+
+ return non_secure == get_gpioz_nbpin();
+}
+
+static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
+{
+ unsigned int secure = 0U;
+ unsigned int i;
+
+ lock_registering();
+
+ if (bank != GPIO_BANK_Z) {
+ return false;
+ }
+
+ for (i = 0U; i < get_gpioz_nbpin(); i++) {
+ if (periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
+ secure++;
+ }
+ }
+
+ return secure == get_gpioz_nbpin();
+}
+
+bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
+{
+ enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
+
+ switch (clock_id) {
+ case CK_CSI:
+ case CK_HSE:
+ case CK_HSE_DIV2:
+ case CK_HSI:
+ case CK_LSE:
+ case CK_LSI:
+ case PLL1_P:
+ case PLL1_Q:
+ case PLL1_R:
+ case PLL2_P:
+ case PLL2_Q:
+ case PLL2_R:
+ case PLL3_P:
+ case PLL3_Q:
+ case PLL3_R:
+ case RTCAPB:
+ return true;
+ case GPIOZ:
+ /* Allow clock access if at least one pin is non-secure */
+ return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z);
+ case CRYP1:
+ shres_id = STM32MP1_SHRES_CRYP1;
+ break;
+ case HASH1:
+ shres_id = STM32MP1_SHRES_HASH1;
+ break;
+ case I2C4_K:
+ shres_id = STM32MP1_SHRES_I2C4;
+ break;
+ case I2C6_K:
+ shres_id = STM32MP1_SHRES_I2C6;
+ break;
+ case IWDG1:
+ shres_id = STM32MP1_SHRES_IWDG1;
+ break;
+ case RNG1_K:
+ shres_id = STM32MP1_SHRES_RNG1;
+ break;
+ case RTC:
+ shres_id = STM32MP1_SHRES_RTC;
+ break;
+ case SPI6_K:
+ shres_id = STM32MP1_SHRES_SPI6;
+ break;
+ case USART1_K:
+ shres_id = STM32MP1_SHRES_USART1;
+ break;
+ default:
+ return false;
+ }
+
+ return periph_is_non_secure(shres_id);
+}
+
bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
{
- return true;
+ enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
+
+ switch (reset_id) {
+ case CRYP1_R:
+ shres_id = STM32MP1_SHRES_CRYP1;
+ break;
+ case GPIOZ_R:
+ /* GPIOZ reset mandates all pins are non-secure */
+ return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
+ case HASH1_R:
+ shres_id = STM32MP1_SHRES_HASH1;
+ break;
+ case I2C4_R:
+ shres_id = STM32MP1_SHRES_I2C4;
+ break;
+ case I2C6_R:
+ shres_id = STM32MP1_SHRES_I2C6;
+ break;
+ case MCU_R:
+ shres_id = STM32MP1_SHRES_MCU;
+ break;
+ case MDMA_R:
+ shres_id = STM32MP1_SHRES_MDMA;
+ break;
+ case RNG1_R:
+ shres_id = STM32MP1_SHRES_RNG1;
+ break;
+ case SPI6_R:
+ shres_id = STM32MP1_SHRES_SPI6;
+ break;
+ case USART1_R:
+ shres_id = STM32MP1_SHRES_USART1;
+ break;
+ default:
+ return false;
+ }
+
+ return periph_is_non_secure(shres_id);
}
static bool mckprot_protects_periph(enum stm32mp_shres id)
@@ -170,10 +541,10 @@
}
if (!secure || (mckprot_protects_periph(n) && (!mckprot))) {
- ERROR("RCC %s MCKPROT %s and %u secure\n",
+ ERROR("RCC %s MCKPROT %s and %s secure\n",
secure ? "secure" : "non-secure",
mckprot ? "set" : "not set",
- n);
+ shres2str_id(n));
error++;
}
}
@@ -201,14 +572,14 @@
for (id = 0U; id < STM32MP1_SHRES_COUNT; id++) {
switch (shres_state[id]) {
case SHRES_SECURE:
- INFO("stm32mp1 %u is secure\n", id);
+ INFO("stm32mp1 %s is secure\n", shres2str_id(id));
break;
case SHRES_NON_SECURE:
case SHRES_UNREGISTERED:
- VERBOSE("stm32mp %u is non-secure\n", id);
+ VERBOSE("stm32mp %s is non-secure\n", shres2str_id(id));
break;
default:
- VERBOSE("stm32mp %u is invalid\n", id);
+ VERBOSE("stm32mp %s is invalid\n", shres2str_id(id));
panic();
}
}
diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c
index 80b498e..8c5b04a 100644
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -24,17 +24,17 @@
#define OPT_ALIGN 2
static int info_cmd(int argc, char *argv[]);
-static void info_usage(void);
+static void info_usage(int);
static int create_cmd(int argc, char *argv[]);
-static void create_usage(void);
+static void create_usage(int);
static int update_cmd(int argc, char *argv[]);
-static void update_usage(void);
+static void update_usage(int);
static int unpack_cmd(int argc, char *argv[]);
-static void unpack_usage(void);
+static void unpack_usage(int);
static int remove_cmd(int argc, char *argv[]);
-static void remove_usage(void);
+static void remove_usage(int);
static int version_cmd(int argc, char *argv[]);
-static void version_usage(void);
+static void version_usage(int);
static int help_cmd(int argc, char *argv[]);
static void usage(void);
@@ -448,7 +448,7 @@
fip_toc_header_t toc_header;
if (argc != 2)
- info_usage();
+ info_usage(EXIT_FAILURE);
argc--, argv++;
parse_fip(argv[0], &toc_header);
@@ -487,10 +487,10 @@
return 0;
}
-static void info_usage(void)
+static void info_usage(int exit_status)
{
printf("fiptool info FIP_FILENAME\n");
- exit(1);
+ exit(exit_status);
}
static int pack_images(const char *filename, uint64_t toc_flags, unsigned long align)
@@ -669,7 +669,7 @@
unsigned long align = 1;
if (argc < 2)
- create_usage();
+ create_usage(EXIT_FAILURE);
opts = fill_common_opts(opts, &nr_opts, required_argument);
opts = add_opt(opts, &nr_opts, "plat-toc-flags", required_argument,
@@ -710,7 +710,7 @@
if (memcmp(&uuid, &uuid_null, sizeof(uuid_t)) == 0 ||
filename[0] == '\0')
- create_usage();
+ create_usage(EXIT_FAILURE);
desc = lookup_image_desc_from_uuid(&uuid);
if (desc == NULL) {
@@ -722,7 +722,7 @@
break;
}
default:
- create_usage();
+ create_usage(EXIT_FAILURE);
}
}
argc -= optind;
@@ -730,7 +730,7 @@
free(opts);
if (argc == 0)
- create_usage();
+ create_usage(EXIT_SUCCESS);
update_fip();
@@ -738,7 +738,7 @@
return 0;
}
-static void create_usage(void)
+static void create_usage(int exit_status)
{
toc_entry_t *toc_entry = toc_entries;
@@ -753,7 +753,7 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
- exit(1);
+ exit(exit_status);
}
static int update_cmd(int argc, char *argv[])
@@ -767,7 +767,7 @@
int pflag = 0;
if (argc < 2)
- update_usage();
+ update_usage(EXIT_FAILURE);
opts = fill_common_opts(opts, &nr_opts, required_argument);
opts = add_opt(opts, &nr_opts, "align", required_argument, OPT_ALIGN);
@@ -807,7 +807,7 @@
if (memcmp(&uuid, &uuid_null, sizeof(uuid_t)) == 0 ||
filename[0] == '\0')
- update_usage();
+ update_usage(EXIT_FAILURE);
desc = lookup_image_desc_from_uuid(&uuid);
if (desc == NULL) {
@@ -825,7 +825,7 @@
snprintf(outfile, sizeof(outfile), "%s", optarg);
break;
default:
- update_usage();
+ update_usage(EXIT_FAILURE);
}
}
argc -= optind;
@@ -833,7 +833,7 @@
free(opts);
if (argc == 0)
- update_usage();
+ update_usage(EXIT_SUCCESS);
if (outfile[0] == '\0')
snprintf(outfile, sizeof(outfile), "%s", argv[0]);
@@ -851,7 +851,7 @@
return 0;
}
-static void update_usage(void)
+static void update_usage(int exit_status)
{
toc_entry_t *toc_entry = toc_entries;
@@ -867,7 +867,7 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
- exit(1);
+ exit(exit_status);
}
static int unpack_cmd(int argc, char *argv[])
@@ -880,7 +880,7 @@
int unpack_all = 1;
if (argc < 2)
- unpack_usage();
+ unpack_usage(EXIT_FAILURE);
opts = fill_common_opts(opts, &nr_opts, required_argument);
opts = add_opt(opts, &nr_opts, "blob", required_argument, 'b');
@@ -915,7 +915,7 @@
if (memcmp(&uuid, &uuid_null, sizeof(uuid_t)) == 0 ||
filename[0] == '\0')
- unpack_usage();
+ unpack_usage(EXIT_FAILURE);
desc = lookup_image_desc_from_uuid(&uuid);
if (desc == NULL) {
@@ -934,7 +934,7 @@
snprintf(outdir, sizeof(outdir), "%s", optarg);
break;
default:
- unpack_usage();
+ unpack_usage(EXIT_FAILURE);
}
}
argc -= optind;
@@ -942,7 +942,7 @@
free(opts);
if (argc == 0)
- unpack_usage();
+ unpack_usage(EXIT_SUCCESS);
parse_fip(argv[0], NULL);
@@ -986,7 +986,7 @@
return 0;
}
-static void unpack_usage(void)
+static void unpack_usage(int exit_status)
{
toc_entry_t *toc_entry = toc_entries;
@@ -1003,7 +1003,7 @@
toc_entry->name);
printf("\n");
printf("If no options are provided, all images will be unpacked.\n");
- exit(1);
+ exit(exit_status);
}
static int remove_cmd(int argc, char *argv[])
@@ -1017,7 +1017,7 @@
int fflag = 0;
if (argc < 2)
- remove_usage();
+ remove_usage(EXIT_FAILURE);
opts = fill_common_opts(opts, &nr_opts, no_argument);
opts = add_opt(opts, &nr_opts, "align", required_argument, OPT_ALIGN);
@@ -1053,7 +1053,7 @@
filename, sizeof(filename));
if (memcmp(&uuid, &uuid_null, sizeof(uuid_t)) == 0)
- remove_usage();
+ remove_usage(EXIT_FAILURE);
desc = lookup_image_desc_from_uuid(&uuid);
if (desc == NULL) {
@@ -1071,7 +1071,7 @@
snprintf(outfile, sizeof(outfile), "%s", optarg);
break;
default:
- remove_usage();
+ remove_usage(EXIT_FAILURE);
}
}
argc -= optind;
@@ -1079,7 +1079,7 @@
free(opts);
if (argc == 0)
- remove_usage();
+ remove_usage(EXIT_SUCCESS);
if (outfile[0] != '\0' && access(outfile, F_OK) == 0 && !fflag)
log_errx("File %s already exists, use --force to overwrite it",
@@ -1110,7 +1110,7 @@
return 0;
}
-static void remove_usage(void)
+static void remove_usage(int exit_status)
{
toc_entry_t *toc_entry = toc_entries;
@@ -1126,7 +1126,7 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
- exit(1);
+ exit(exit_status);
}
static int version_cmd(int argc, char *argv[])
@@ -1140,10 +1140,10 @@
return 0;
}
-static void version_usage(void)
+static void version_usage(int exit_status)
{
printf("fiptool version\n");
- exit(1);
+ exit(exit_status);
}
static int help_cmd(int argc, char *argv[])
@@ -1157,7 +1157,7 @@
for (i = 0; i < NELEM(cmds); i++) {
if (strcmp(cmds[i].name, argv[0]) == 0 &&
cmds[i].usage != NULL)
- cmds[i].usage();
+ cmds[i].usage(EXIT_SUCCESS);
}
if (i == NELEM(cmds))
printf("No help for subcommand '%s'\n", argv[0]);
@@ -1178,7 +1178,7 @@
printf(" remove\tRemove images from FIP.\n");
printf(" version\tShow fiptool version.\n");
printf(" help\t\tShow help for given command.\n");
- exit(1);
+ exit(EXIT_SUCCESS);
}
int main(int argc, char *argv[])
diff --git a/tools/fiptool/fiptool.h b/tools/fiptool/fiptool.h
index af3fcbd..88c4a7e 100644
--- a/tools/fiptool/fiptool.h
+++ b/tools/fiptool/fiptool.h
@@ -48,7 +48,7 @@
typedef struct cmd {
char *name;
int (*handler)(int, char **);
- void (*usage)(void);
+ void (*usage)(int);
} cmd_t;
#endif /* FIPTOOL_H */