tree b29d2d6e9716d503cd8458a6d21a62b7b515c634
parent 88a8cd0e542ea1eaa92dcd8b5f6115dc9ed8d525
author Bipin Ravi <bipin.ravi@arm.com> 1703104322 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1706533585 +0000

fix(cpus): workaround for Cortex-X3 erratum 2302506

Cortex-X3 erratum 2302506 is a cat B erratum that applies to
revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to
set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave
like PLD/PRFM LD and not cause invalidation to other PE caches.

There might be a small performance degradation to this workaround
for certain workloads that share data.

SDEN can be found here:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I048b830867915b88afa36582c6da05734a56d22a
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>