refactor(cpufeat): enable FEAT_CSV2_2 for FEAT_STATE_CHECKED
At the moment we only support FEAT_CSV2_2 to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_CSV2_2=2), by splitting
is_armv8_0_feat_csv2_2_present() into an ID register reading function
and a second function to report the support status. That function
considers both build time settings and runtime information (if needed),
and is used before we access the SCXTNUM_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_csv2_2_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I89c7bc883e6a65727fdbdd36eb3bfbffb2196da7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index cf4bb30..8430c06 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -171,10 +171,10 @@
scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
-#if ENABLE_FEAT_CSV2_2
- /* Enable access to the SCXTNUM_ELx registers. */
- scr_el3 |= SCR_EnSCXT_BIT;
-#endif
+ if (is_feat_csv2_2_supported()) {
+ /* Enable access to the SCXTNUM_ELx registers. */
+ scr_el3 |= SCR_EnSCXT_BIT;
+ }
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@@ -227,10 +227,10 @@
scr_el3 |= SCR_TERR_BIT;
#endif
-#if ENABLE_FEAT_CSV2_2
- /* Enable access to the SCXTNUM_ELx registers. */
- scr_el3 |= SCR_EnSCXT_BIT;
-#endif
+ if (is_feat_csv2_2_supported()) {
+ /* Enable access to the SCXTNUM_ELx registers. */
+ scr_el3 |= SCR_EnSCXT_BIT;
+ }
#ifdef IMAGE_BL31
/*
@@ -976,9 +976,12 @@
if (is_feat_trf_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2());
}
-#if ENABLE_FEAT_CSV2_2
- el2_sysregs_context_save_csv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_csv2_2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2,
+ read_scxtnum_el2());
+ }
+
if (is_feat_hcx_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2());
}
@@ -1039,9 +1042,12 @@
if (is_feat_trf_supported()) {
write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2));
}
-#if ENABLE_FEAT_CSV2_2
- el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_csv2_2_supported()) {
+ write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx,
+ CTX_SCXTNUM_EL2));
+ }
+
if (is_feat_hcx_supported()) {
write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2));
}