Unify SCTLR initialization for AArch32 normal world
The values of CP15BEN, nTWI & nTWE bits in SCTLR_EL1 are architecturally
unknown if EL3 is AARCH64 whereas they reset to 1 if EL3 is AArch32. This
might be a compatibility break for legacy AArch32 normal world software if
these bits are not set to 1 when EL3 is AArch64. This patch enables the
CP15BEN, nTWI and nTWE bits in the SCTLR_EL1 if the lower non-secure EL is
AArch32. This unifies the SCTLR settings for lower non-secure EL in AArch32
mode for both AArch64 and AArch32 builds of Trusted Firmware.
Fixes ARM-software/tf-issues#428
Change-Id: I3152d1580e4869c0ea745c5bd9da765f9c254947
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index bc5f9c4..02ae2a7 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -116,7 +116,12 @@
*/
if (security_state != SECURE) {
sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
- sctlr |= SCTLR_RES1;
+ /*
+ * In addition to SCTLR_RES1, set the CP15_BEN, nTWI & nTWE
+ * bits that architecturally reset to 1.
+ */
+ sctlr |= SCTLR_RES1 | SCTLR_CP15BEN_BIT |
+ SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
}