refactor(cpufeat): enable FEAT_ECV for FEAT_STATE_CHECKED
At the moment we only support FEAT_ECV to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_FEAT_ECV=2), by splitting
is_feat_ecv_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access the CNTPOFF_EL2 system register.
Also move the context saving code from assembly to C, and use the new
is_feat_ecv_supported() function to guard its execution.
Change the FVP platform default to the now supported dynamic option (=2),
so the right decision can be made by the code at runtime.
Change-Id: I4acd5384929f1902b62a87ae073aafa1472cd66b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index a5b64a5..baabd3b 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -17,10 +17,6 @@
.global el2_sysregs_context_save_mte
.global el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if ENABLE_FEAT_ECV
- .global el2_sysregs_context_save_ecv
- .global el2_sysregs_context_restore_ecv
-#endif /* ENABLE_FEAT_ECV */
#if RAS_EXTENSION
.global el2_sysregs_context_save_ras
.global el2_sysregs_context_restore_ras
@@ -222,20 +218,6 @@
endfunc el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if ENABLE_FEAT_ECV
-func el2_sysregs_context_save_ecv
- mrs x11, CNTPOFF_EL2
- str x11, [x0, #CTX_CNTPOFF_EL2]
- ret
-endfunc el2_sysregs_context_save_ecv
-
-func el2_sysregs_context_restore_ecv
- ldr x11, [x0, #CTX_CNTPOFF_EL2]
- msr CNTPOFF_EL2, x11
- ret
-endfunc el2_sysregs_context_restore_ecv
-#endif /* ENABLE_FEAT_ECV */
-
#if RAS_EXTENSION
func el2_sysregs_context_save_ras
/*
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index c91070e..cf4bb30 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -380,8 +380,7 @@
scr_el3 |= SCR_FGTEN_BIT;
}
- if (get_armv8_6_ecv_support()
- == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
+ if (is_feat_ecv_supported()) {
scr_el3 |= SCR_ECVEN_BIT;
}
}
@@ -957,9 +956,11 @@
el2_sysregs_context_save_fgt(el2_sysregs_ctx);
}
-#if ENABLE_FEAT_ECV
- el2_sysregs_context_save_ecv(el2_sysregs_ctx);
-#endif
+ if (is_feat_ecv_v2_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2,
+ read_cntpoff_el2());
+ }
+
if (is_feat_vhe_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2,
read_contextidr_el2());
@@ -1020,9 +1021,11 @@
el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
}
-#if ENABLE_FEAT_ECV
- el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
-#endif
+ if (is_feat_ecv_v2_supported()) {
+ write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx,
+ CTX_CNTPOFF_EL2));
+ }
+
if (is_feat_vhe_supported()) {
write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2));
write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2));