diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index bcba60a..ea11708 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -34,6 +34,6 @@
 	fvp_interconnect_enable();
 
 	/* On FVP RevC, intialize SMMUv3 */
-	if (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3)
+	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
 		smmuv3_init(PLAT_FVP_SMMUV3_BASE);
 }
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index c7c45b0..4e16e3b 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -16,8 +16,6 @@
 #include <platform.h>
 #include <ras.h>
 
-#define BL31_END (uintptr_t)(&__BL31_END__)
-
 /*
  * Placeholder variables for copying the arguments that have been passed to
  * BL31 from BL2.
@@ -152,7 +150,7 @@
 	 * Copy BL33 and BL32 (if present), entry point information.
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
-	while (bl_params) {
+	while (bl_params != NULL) {
 		if (bl_params->image_id == BL32_IMAGE_ID)
 			bl32_image_ep_info = *bl_params->ep_info;
 
@@ -162,7 +160,7 @@
 		bl_params = bl_params->next_params_info;
 	}
 
-	if (bl33_image_ep_info.pc == 0)
+	if (bl33_image_ep_info.pc == 0U)
 		panic();
 
 # else /* LOAD_IMAGE_V2 */
@@ -175,8 +173,8 @@
 	assert(from_bl2->h.version >= VERSION_1);
 
 	/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
-	assert(soc_fw_config == 0);
-	assert(hw_config == 0);
+	assert(soc_fw_config == 0U);
+	assert(hw_config == 0U);
 
 	/*
 	 * Copy BL32 (if populated by BL2) and BL33 entry point information.
@@ -236,7 +234,7 @@
 
 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0) | CNTCR_EN);
+			CNTCR_FCREQ(0U) | CNTCR_EN);
 
 	/* Allow access to the System counter timer module */
 	arm_configure_sys_timer();
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 5191d69..10c1914 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -5,6 +5,7 @@
  */
 
 #include <assert.h>
+#include <bl_common.h>
 #include <console.h>
 #include <debug.h>
 #include <mmio.h>
@@ -13,8 +14,6 @@
 #include <platform_def.h>
 #include <platform_sp_min.h>
 
-#define BL32_END (uintptr_t)(&__BL32_END__)
-
 static entry_point_info_t bl33_image_ep_info;
 
 /* Weak definitions may be overridden in specific ARM standard platform */
@@ -181,7 +180,7 @@
 
 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
-			CNTCR_FCREQ(0) | CNTCR_EN);
+			CNTCR_FCREQ(0U) | CNTCR_EN);
 
 	/* Allow access to the System counter timer module */
 	arm_configure_sys_timer();