diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 9914f12..ef760ed 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -31,7 +31,7 @@
 	bl	check_errata_1688305
 	cbz	x0, 1f
 	mrs     x1, CORTEX_A78_ACTLR2_EL1
-	orr	x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
+	orr	x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
 	msr     CORTEX_A78_ACTLR2_EL1, x1
 	isb
 1:
@@ -44,6 +44,34 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_1688305
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A78 Errata #1941498.
+	 * This applies to revisions r0p0, r1p0, and r1p1.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a78_1941498_wa
+	/* Compare x0 against revision <= r1p1 */
+	mov	x17, x30
+	bl	check_errata_1941498
+	cbz	x0, 1f
+
+	/* Set bit 8 in ECTLR_EL1 */
+	mrs	x1, CORTEX_A78_CPUECTLR_EL1
+	orr	x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
+	msr	CORTEX_A78_CPUECTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a78_1941498_wa
+
+func check_errata_1941498
+	/* Check for revision <= r1p1, might need to be updated later. */
+	mov	x1, #0x11
+	b	cpu_rev_var_ls
+endfunc check_errata_1941498
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A78
 	 * -------------------------------------------------
@@ -58,6 +86,11 @@
 	bl	errata_a78_1688305_wa
 #endif
 
+#if ERRATA_A78_1941498
+	mov     x0, x18
+	bl	errata_a78_1941498_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -113,6 +146,7 @@
 	 * checking functions of each errata.
 	 */
 	report_errata ERRATA_A78_1688305, cortex_a78, 1688305
+	report_errata ERRATA_A78_1941498, cortex_a78, 1941498
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index da0157f..b7dec0b 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
 # Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -294,6 +294,10 @@
 # to revisions r0p0 - r1p0 of the A78 cpu.
 ERRATA_A78_1688305	?=0
 
+# Flag to apply erratum 1941498 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1 of the A78 cpu.
+ERRATA_A78_1941498	?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=0
@@ -575,6 +579,10 @@
 $(eval $(call assert_boolean,ERRATA_A78_1688305))
 $(eval $(call add_define,ERRATA_A78_1688305))
 
+# Process ERRATA_A78_1941498 flag
+$(eval $(call assert_boolean,ERRATA_A78_1941498))
+$(eval $(call add_define,ERRATA_A78_1941498))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))