TFTF: Add missing D-cache invalidation
This patch adds missing D-cache invalidation of RW memory
in tftf_entrypoint to safeguard against possible corruption
of this memory by dirty cache lines in a system cache as
a result of use by an earlier boot loader stage.
Ref. GENFW-3455
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Change-Id: I595344c307502a6c24c2e62d3e3f2f9d7a810dfa
diff --git a/tftf/framework/aarch32/entrypoint.S b/tftf/framework/aarch32/entrypoint.S
index 1f302fa..eaa0788 100644
--- a/tftf/framework/aarch32/entrypoint.S
+++ b/tftf/framework/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,18 @@
bl arch_init
/* --------------------------------------------------------------------
+ * Invalidate the RW memory used by TFTF image.
+ * This is done to safeguard against possible corruption of this
+ * memory by dirty cache lines in a system cache as a result of use
+ * by an earlier boot loader stage.
+ * --------------------------------------------------------------------
+ */
+ ldr r0, =__DATA_START__
+ ldr r1, =__DATA_END__
+ sub r1, r1, r0
+ bl inv_dcache_range
+
+ /* --------------------------------------------------------------------
* This code is expected to be executed only by the primary CPU.
* Save the mpid for the first core that executes and if a secondary
* CPU has lost its way make it spin forever.