| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 1 | /* |
| Alexei Fedorov | 86c3e44 | 2020-07-17 17:03:25 +0100 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, Arm Limited. All rights reserved. |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <assert_macros.S> |
| 10 | |
| 11 | .globl zeromem |
| 12 | .globl memcpy4 |
| 13 | .globl disable_mmu_icache |
| 14 | |
| 15 | /* ----------------------------------------------------------------------- |
| 16 | * void zeromem(void *mem, unsigned int length); |
| 17 | * |
| 18 | * Initialise a memory region to 0. |
| Alexei Fedorov | 86c3e44 | 2020-07-17 17:03:25 +0100 | [diff] [blame] | 19 | * The memory address must be 4-byte aligned. |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 20 | * ----------------------------------------------------------------------- |
| 21 | */ |
| 22 | func zeromem |
| 23 | #if ENABLE_ASSERTIONS |
| 24 | tst r0, #0x3 |
| 25 | ASM_ASSERT(eq) |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 26 | #endif |
| Alexei Fedorov | 86c3e44 | 2020-07-17 17:03:25 +0100 | [diff] [blame] | 27 | mov r2, #0 |
| 28 | /* zero 4 bytes at a time */ |
| 29 | z_loop4: |
| 30 | cmp r1, #4 |
| 31 | blo z_loop1 |
| 32 | str r2, [r0], #4 |
| 33 | subs r1, r1, #4 |
| 34 | bne z_loop4 |
| 35 | bx lr |
| 36 | |
| 37 | /* zero byte per byte */ |
| 38 | z_loop1: |
| 39 | strb r2, [r0], #1 |
| 40 | subs r1, r1, #1 |
| 41 | bne z_loop1 |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 42 | bx lr |
| 43 | endfunc zeromem |
| 44 | |
| 45 | /* -------------------------------------------------------------------------- |
| 46 | * void memcpy4(void *dest, const void *src, unsigned int length) |
| 47 | * |
| 48 | * Copy length bytes from memory area src to memory area dest. |
| 49 | * The memory areas should not overlap. |
| 50 | * Destination and source addresses must be 4-byte aligned. |
| 51 | * -------------------------------------------------------------------------- |
| 52 | */ |
| 53 | func memcpy4 |
| 54 | #if ASM_ASSERTION |
| 55 | orr r3, r0, r1 |
| 56 | tst r3, #0x3 |
| 57 | ASM_ASSERT(eq) |
| 58 | #endif |
| 59 | /* copy 4 bytes at a time */ |
| 60 | m_loop4: |
| 61 | cmp r2, #4 |
| Alexei Fedorov | 86c3e44 | 2020-07-17 17:03:25 +0100 | [diff] [blame] | 62 | blo m_loop1 |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 63 | ldr r3, [r1], #4 |
| 64 | str r3, [r0], #4 |
| Alexei Fedorov | 86c3e44 | 2020-07-17 17:03:25 +0100 | [diff] [blame] | 65 | subs r2, r2, #4 |
| 66 | bne m_loop4 |
| 67 | bx lr |
| 68 | |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 69 | /* copy byte per byte */ |
| 70 | m_loop1: |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 71 | ldrb r3, [r1], #1 |
| 72 | strb r3, [r0], #1 |
| 73 | subs r2, r2, #1 |
| 74 | bne m_loop1 |
| Sandrine Bailleux | 3cd87d7 | 2018-10-09 11:12:55 +0200 | [diff] [blame] | 75 | bx lr |
| 76 | endfunc memcpy4 |
| 77 | |
| 78 | /* --------------------------------------------------------------------------- |
| 79 | * Disable the MMU in Secure State |
| 80 | * --------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | func disable_mmu |
| 84 | mov r1, #(HSCTLR_M_BIT | HSCTLR_C_BIT) |
| 85 | do_disable_mmu: |
| 86 | ldcopr r0, HSCTLR |
| 87 | bic r0, r0, r1 |
| 88 | stcopr r0, HSCTLR |
| 89 | isb // ensure MMU is off |
| 90 | dsb sy |
| 91 | bx lr |
| 92 | endfunc disable_mmu |
| 93 | |
| 94 | |
| 95 | func disable_mmu_icache |
| 96 | ldr r1, =(HSCTLR_M_BIT | HSCTLR_C_BIT | HSCTLR_I_BIT) |
| 97 | b do_disable_mmu |
| 98 | endfunc disable_mmu_icache |