blob: 02fadb35e620b7e9b3d990783f8fd7d0804dfd69 [file] [log] [blame]
Varun Wadekardbf8a2f2020-06-23 08:13:57 -07001/*
2 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <assert.h>
9#include <plat_topology.h>
10#include <stddef.h>
11
12#include <tftf_lib.h>
13#include <platform_def.h>
14
15static const struct {
16 unsigned cluster_id;
17 unsigned cpu_id;
18} tegra186_cores[] = {
19 { 0, 0 },
20 { 0, 1 },
21 { 1, 0 },
22 { 1, 1 },
23 { 1, 2 },
24 { 1, 3 }
25};
26
27/*
28 * The Tegra186 power domain tree descriptor. Tegra186 implements a system
29 * power domain at the level 2. The first entry in the power domain descriptor
30 * specifies the number of power domains at the highest power level.
31 */
32static const unsigned char tegra186_power_domain_tree_desc[] = {
33 /* Number of root nodes */
34 PLATFORM_SYSTEM_COUNT,
35 /* Number of children of root node */
36 PLATFORM_CLUSTER_COUNT,
37 /* Number of children for the first cluster */
38 PLATFORM_CORES_CLUSTER0,
39 /* Number of children for the second cluster */
40 PLATFORM_CORES_CLUSTER1
41};
42
43const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
44{
45 return tegra186_power_domain_tree_desc;
46}
47
48uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
49{
50 assert(core_pos < PLATFORM_CORE_COUNT);
51
52 return (uint64_t)make_mpid(tegra186_cores[core_pos].cluster_id,
53 tegra186_cores[core_pos].cpu_id);
54}