PSCI: Add framework to handle composite power states
The state-id field in the power-state parameter of a CPU_SUSPEND call can be
used to describe composite power states specific to a platform. The current PSCI
implementation does not interpret the state-id field. It relies on the target
power level and the state type fields in the power-state parameter to perform
state coordination and power management operations. The framework introduced
in this patch allows the PSCI implementation to intepret generic global states
like RUN, RETENTION or OFF from the State-ID to make global state coordination
decisions and reduce the complexity of platform ports. It adds support to
involve the platform in state coordination which facilitates the use of
composite power states and improves the support for entering standby states
at multiple power domains.
The patch also includes support for extended state-id format for the power
state parameter as specified by PSCIv1.0.
The PSCI implementation now defines a generic representation of the power-state
parameter. It depends on the platform port to convert the power-state parameter
(possibly encoding a composite power state) passed in a CPU_SUSPEND call to this
representation via the `validate_power_state()` plat_psci_ops handler. It is an
array where each index corresponds to a power level. Each entry contains the
local power state the power domain at that power level could enter.
The meaning of the local power state values is platform defined, and may vary
between levels in a single platform. The PSCI implementation constrains the
values only so that it can classify the state as RUN, RETENTION or OFF as
required by the specification:
* zero means RUN
* all OFF state values at all levels must be higher than all RETENTION
state values at all levels
* the platform provides PLAT_MAX_RET_STATE and PLAT_MAX_OFF_STATE values
to the framework
The platform also must define the macros PLAT_MAX_RET_STATE and
PLAT_MAX_OFF_STATE which lets the PSCI implementation find out which power
domains have been requested to enter a retention or power down state. The PSCI
implementation does not interpret the local power states defined by the
platform. The only constraint is that the PLAT_MAX_RET_STATE <
PLAT_MAX_OFF_STATE.
For a power domain tree, the generic implementation maintains an array of local
power states. These are the states requested for each power domain by all the
cores contained within the domain. During a request to place multiple power
domains in a low power state, the platform is passed an array of requested
power-states for each power domain through the plat_get_target_pwr_state()
API. It coordinates amongst these states to determine a target local power
state for the power domain. A default weak implementation of this API is
provided in the platform layer which returns the minimum of the requested
power-states back to the PSCI state coordination.
Finally, the plat_psci_ops power management handlers are passed the target
local power states for each affected power domain using the generic
representation described above. The platform executes operations specific to
these target states.
The platform power management handler for placing a power domain in a standby
state (plat_pm_ops_t.pwr_domain_standby()) is now only used as a fast path for
placing a core power domain into a standby or retention state should now be
used to only place the core power domain in a standby or retention state.
The extended state-id power state format can be enabled by setting the
build flag PSCI_EXTENDED_STATE_ID=1 and it is disabled by default.
Change-Id: I9d4123d97e179529802c1f589baaa4101759d80c
diff --git a/services/std_svc/psci1.0/psci_on.c b/services/std_svc/psci1.0/psci_on.c
index c85e349..542cc23 100644
--- a/services/std_svc/psci1.0/psci_on.c
+++ b/services/std_svc/psci1.0/psci_on.c
@@ -44,19 +44,37 @@
* This function checks whether a cpu which has been requested to be turned on
* is OFF to begin with.
******************************************************************************/
-static int cpu_on_validate_state(unsigned int psci_state)
+static int cpu_on_validate_state(aff_info_state_t aff_state)
{
- if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND)
+ if (aff_state == AFF_STATE_ON)
return PSCI_E_ALREADY_ON;
- if (psci_state == PSCI_STATE_ON_PENDING)
+ if (aff_state == AFF_STATE_ON_PENDING)
return PSCI_E_ON_PENDING;
- assert(psci_state == PSCI_STATE_OFF);
+ assert(aff_state == AFF_STATE_OFF);
return PSCI_E_SUCCESS;
}
/*******************************************************************************
+ * This function sets the aff_info_state in the per-cpu data of the CPU
+ * specified by cpu_idx
+ ******************************************************************************/
+static void psci_set_aff_info_state_by_idx(unsigned int cpu_idx,
+ aff_info_state_t aff_state)
+{
+
+ set_cpu_data_by_index(cpu_idx,
+ psci_svc_cpu_data.aff_info_state,
+ aff_state);
+
+ /*
+ * Flush aff_info_state as it will be accessed with caches turned OFF.
+ */
+ flush_cpu_data_by_index(cpu_idx, psci_svc_cpu_data.aff_info_state);
+}
+
+/*******************************************************************************
* Generic handler which is called to physically power on a cpu identified by
* its mpidr. It performs the generic, architectural, platform setup and state
* management to power on the target cpu e.g. it will ensure that
@@ -67,8 +85,8 @@
* platform handler as it can return error.
******************************************************************************/
int psci_cpu_on_start(unsigned long target_cpu,
- entry_point_info_t *ep,
- int end_pwrlvl)
+ entry_point_info_t *ep,
+ int end_pwrlvl)
{
int rc;
unsigned long psci_entrypoint;
@@ -88,7 +106,7 @@
* Generic management: Ensure that the cpu is off to be
* turned on.
*/
- rc = cpu_on_validate_state(psci_get_state(target_idx, PSCI_CPU_PWR_LVL));
+ rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
if (rc != PSCI_E_SUCCESS)
goto exit;
@@ -101,13 +119,9 @@
psci_spd_pm->svc_on(target_cpu);
/*
- * This function updates the state of each affinity instance
- * corresponding to the mpidr in the range of power domain levels
- * specified.
+ * Set the Affinity info state of the target cpu to ON_PENDING.
*/
- psci_do_state_coordination(end_pwrlvl,
- target_idx,
- PSCI_STATE_ON_PENDING);
+ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
/*
* Perform generic, architecture and platform specific handling.
@@ -120,9 +134,8 @@
* of the target cpu to allow it to perform the necessary
* steps to power on.
*/
- rc = psci_plat_pm_ops->pwr_domain_on(target_cpu,
- psci_entrypoint,
- MPIDR_AFFLVL0);
+ rc = psci_plat_pm_ops->pwr_domain_on((u_register_t)target_cpu,
+ psci_entrypoint);
assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
if (rc == PSCI_E_SUCCESS)
@@ -130,9 +143,7 @@
cm_init_context_by_index(target_idx, ep);
else
/* Restore the state on error. */
- psci_do_state_coordination(end_pwrlvl,
- target_idx,
- PSCI_STATE_OFF);
+ psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
exit:
psci_spin_unlock_cpu(target_idx);
@@ -141,22 +152,19 @@
/*******************************************************************************
* The following function finish an earlier power on request. They
- * are called by the common finisher routine in psci_common.c.
+ * are called by the common finisher routine in psci_common.c. The `state_info`
+ * is the psci_power_state from which this CPU has woken up from.
******************************************************************************/
void psci_cpu_on_finish(unsigned int cpu_idx,
- int max_off_pwrlvl)
+ psci_power_state_t *state_info)
{
- /* Ensure we have been explicitly woken up by another cpu */
- assert(psci_get_state(cpu_idx, PSCI_CPU_PWR_LVL)
- == PSCI_STATE_ON_PENDING);
-
/*
* Plat. management: Perform the platform specific actions
* for this cpu e.g. enabling the gic or zeroing the mailbox
* register. The actual state of this cpu has already been
* changed.
*/
- psci_plat_pm_ops->pwr_domain_on_finish(max_off_pwrlvl);
+ psci_plat_pm_ops->pwr_domain_on_finish(state_info);
/*
* Arch. management: Enable data cache and manage stack memory
@@ -179,6 +187,9 @@
psci_spin_lock_cpu(cpu_idx);
psci_spin_unlock_cpu(cpu_idx);
+ /* Ensure we have been explicitly woken up by another cpu */
+ assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING);
+
/*
* Call the cpu on finish handler registered by the Secure Payload
* Dispatcher to let it do any bookeeping. If the handler encounters an