stm32mp1: use new functions to manage timeouts
Remove the previously use function: get_timer, and use new functions
timeout_init_us and timeout_elapsed.
Change-Id: I4e95b123648bff7ca91e40462a2a3ae24cfe1697
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 26a5a4d..9db0c5d 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -29,7 +29,7 @@
#define INVALID_OFFSET 0xFFU
-#define TIMESLOT_1US (plat_get_syscnt_freq2() / 1000000U)
+#define TIMEOUT_US_1S 1000000U
#define DDRCTL_REG(x, y) \
{ \
@@ -324,49 +324,43 @@
{
uint32_t pgsr;
int error = 0;
- unsigned long start;
- unsigned long time0, time;
-
- start = get_timer(0);
- time0 = start;
+ uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
do {
pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
- time = get_timer(start);
- if (time != time0) {
- VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
- (uintptr_t)&phy->pgsr, pgsr);
- VERBOSE(" [0x%lx] pir = 0x%x (time=%lx)\n",
- (uintptr_t)&phy->pir,
- mmio_read_32((uintptr_t)&phy->pir),
- time);
- }
- time0 = time;
- if (time > plat_get_syscnt_freq2()) {
+ VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
+ (uintptr_t)&phy->pgsr, pgsr);
+
+ if (timeout_elapsed(timeout)) {
panic();
}
+
if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) {
VERBOSE("DQS Gate Trainig Error\n");
error++;
}
+
if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) {
VERBOSE("DQS Gate Trainig Intermittent Error\n");
error++;
}
+
if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) {
VERBOSE("DQS Drift Error\n");
error++;
}
+
if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) {
VERBOSE("Read Valid Training Error\n");
error++;
}
+
if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) {
VERBOSE("Read Valid Training Intermittent Error\n");
error++;
}
- } while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0);
+ } while (((pgsr & DDRPHYC_PGSR_IDONE) == 0U) && (error == 0));
VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
(uintptr_t)&phy->pgsr, pgsr);
}
@@ -398,21 +392,19 @@
/* Wait quasi dynamic register update */
static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
{
- unsigned long start;
+ uint64_t timeout;
uint32_t swstat;
mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
VERBOSE("[0x%lx] swctl = 0x%x\n",
(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
- start = get_timer(0);
+ timeout = timeout_init_us(TIMEOUT_US_1S);
do {
swstat = mmio_read_32((uintptr_t)&ctl->swstat);
VERBOSE("[0x%lx] swstat = 0x%x ",
(uintptr_t)&ctl->swstat, swstat);
- VERBOSE("timer in ms 0x%x = start 0x%lx\r",
- get_timer(0), start);
- if (get_timer(start) > plat_get_syscnt_freq2()) {
+ if (timeout_elapsed(timeout)) {
panic();
}
} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
@@ -424,22 +416,21 @@
/* Wait quasi dynamic register update */
static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
{
- unsigned long start;
+ uint64_t timeout;
uint32_t stat;
- uint32_t operating_mode;
- uint32_t selref_type;
int break_loop = 0;
- start = get_timer(0);
+ timeout = timeout_init_us(TIMEOUT_US_1S);
for ( ; ; ) {
+ uint32_t operating_mode;
+ uint32_t selref_type;
+
stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
VERBOSE("[0x%lx] stat = 0x%x\n",
(uintptr_t)&priv->ctl->stat, stat);
- VERBOSE("timer in ms 0x%x = start 0x%lx\r",
- get_timer(0), start);
- if (get_timer(start) > plat_get_syscnt_freq2()) {
+ if (timeout_elapsed(timeout)) {
panic();
}