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review.trustedfirmware.org / TF-A / trusted-firmware-a / 0258840e42d0d842e989835aca5b85f417d330ef / . / plat / nvidia / tegra / include / t186 / tegra_def.h
blob: 01da884f7b85913d963d78cec6a85c16f6b9f9ff [file] [log] [blame]
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]1/*
Varun Wadekar50cd8642015-12-28 18:12:59 -0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]34/*******************************************************************************
Varun Wadekardec349c2016-12-12 14:24:17 -0800[diff] [blame]35 * MCE apertures used by the ARI interface
36 *
37 * Aperture 0 - Cpu0 (ARM Cortex A-57)
38 * Aperture 1 - Cpu1 (ARM Cortex A-57)
39 * Aperture 2 - Cpu2 (ARM Cortex A-57)
40 * Aperture 3 - Cpu3 (ARM Cortex A-57)
41 * Aperture 4 - Cpu4 (Denver15)
42 * Aperture 5 - Cpu5 (Denver15)
43 ******************************************************************************/
44#define MCE_ARI_APERTURE_0_OFFSET 0x0
45#define MCE_ARI_APERTURE_1_OFFSET 0x10000
46#define MCE_ARI_APERTURE_2_OFFSET 0x20000
47#define MCE_ARI_APERTURE_3_OFFSET 0x30000
48#define MCE_ARI_APERTURE_4_OFFSET 0x40000
49#define MCE_ARI_APERTURE_5_OFFSET 0x50000
50#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
51
52/* number of apertures */
53#define MCE_ARI_APERTURES_MAX 6
54
55/* each ARI aperture is 64KB */
56#define MCE_ARI_APERTURE_SIZE 0x10000
57
58/*******************************************************************************
59 * CPU core id macros for the MCE_ONLINE_CORE ARI
60 ******************************************************************************/
61#define MCE_CORE_ID_MAX 8
62#define MCE_CORE_ID_MASK 0x7
63
64/*******************************************************************************
Varun Wadekar7afd4632016-01-18 19:03:19 -0800[diff] [blame]65 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
66 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
67 * parameter.
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]68 ******************************************************************************/
Varun Wadekar7afd4632016-01-18 19:03:19 -0800[diff] [blame]69#define PSTATE_ID_CORE_IDLE 6
70#define PSTATE_ID_CORE_POWERDN 7
71#define PSTATE_ID_SOC_POWERDN 2
72
73/*******************************************************************************
74 * Platform power states (used by PSCI framework)
75 *
76 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
77 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
78 ******************************************************************************/
79#define PLAT_MAX_RET_STATE 1
80#define PLAT_MAX_OFF_STATE 8
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]81
82/*******************************************************************************
83 * Implementation defined ACTLR_EL3 bit definitions
84 ******************************************************************************/
85#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
86#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
87#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
88#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
89#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
90#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
91 ACTLR_EL3_L2ECTLR_BIT | \
92 ACTLR_EL3_L2CTLR_BIT | \
93 ACTLR_EL3_CPUECTLR_BIT | \
94 ACTLR_EL3_CPUACTLR_BIT)
95
96/*******************************************************************************
Varun Wadekar50cd8642015-12-28 18:12:59 -0800[diff] [blame]97 * Secure IRQ definitions
98 ******************************************************************************/
99#define TEGRA186_TOP_WDT_IRQ 49
100#define TEGRA186_AON_WDT_IRQ 50
101
102#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */
103
104/*******************************************************************************
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]105 * Tegra Miscellanous register constants
106 ******************************************************************************/
107#define TEGRA_MISC_BASE 0x00100000
Varun Wadekarbe87d922016-02-17 15:07:49 -0800[diff] [blame]108#define HARDWARE_REVISION_OFFSET 0x4
Varun Wadekarabd3a912016-04-02 15:41:20 -0700[diff] [blame]109
Varun Wadekar50402b12016-03-03 13:52:52 -0800[diff] [blame]110#define MISCREG_PFCFG 0x200C
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]111
112/*******************************************************************************
Varun Wadekare64ce3a2016-03-11 17:18:51 -0800[diff] [blame]113 * Tegra TSA Controller constants
114 ******************************************************************************/
115#define TEGRA_TSA_BASE 0x02400000
116
117/*******************************************************************************
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]118 * Tegra Memory Controller constants
119 ******************************************************************************/
120#define TEGRA_MC_STREAMID_BASE 0x02C00000
121#define TEGRA_MC_BASE 0x02C10000
122
Varun Wadekar02588402016-12-12 16:14:57 -0800[diff] [blame^]123/* TZDRAM carveout configuration registers */
124#define MC_SECURITY_CFG0_0 0x70
125#define MC_SECURITY_CFG1_0 0x74
126#define MC_SECURITY_CFG3_0 0x9BC
127
128/* Video Memory carveout configuration registers */
129#define MC_VIDEO_PROTECT_BASE_HI 0x978
130#define MC_VIDEO_PROTECT_BASE_LO 0x648
131#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
132
133/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
134#define MC_TZRAM_BASE_LO 0x2194
135#define TZRAM_BASE_LO_SHIFT 12
136#define TZRAM_BASE_LO_MASK 0xFFFFF
137#define MC_TZRAM_BASE_HI 0x2198
138#define TZRAM_BASE_HI_SHIFT 0
139#define TZRAM_BASE_HI_MASK 3
140#define MC_TZRAM_SIZE 0x219C
141#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
142
143#define MC_TZRAM_CARVEOUT_CFG 0x2190
144#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
145#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
146#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
147#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
148#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
149#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
150#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
151#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
152#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
153#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
154
155#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8
156#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC
157#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0
158#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4
159#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8
160#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC
161
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]162/*******************************************************************************
163 * Tegra UART Controller constants
164 ******************************************************************************/
165#define TEGRA_UARTA_BASE 0x03100000
166#define TEGRA_UARTB_BASE 0x03110000
167#define TEGRA_UARTC_BASE 0x0C280000
168#define TEGRA_UARTD_BASE 0x03130000
169#define TEGRA_UARTE_BASE 0x03140000
170#define TEGRA_UARTF_BASE 0x03150000
171#define TEGRA_UARTG_BASE 0x0C290000
172
173/*******************************************************************************
Varun Wadekar1eed3832016-05-18 13:39:16 -0700[diff] [blame]174 * Tegra Fuse Controller related constants
175 ******************************************************************************/
176#define TEGRA_FUSE_BASE 0x03820000
177#define OPT_SUBREVISION 0x248
178#define SUBREVISION_MASK 0xFF
179
180/*******************************************************************************
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]181 * GICv2 & interrupt handling related constants
182 ******************************************************************************/
183#define TEGRA_GICD_BASE 0x03881000
184#define TEGRA_GICC_BASE 0x03882000
185
186/*******************************************************************************
Varun Wadekar50402b12016-03-03 13:52:52 -0800[diff] [blame]187 * Security Engine related constants
188 ******************************************************************************/
189#define TEGRA_SE0_BASE 0x03AC0000
190#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
191#define TEGRA_PKA1_BASE 0x03AD0000
192#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
193#define TEGRA_RNG1_BASE 0x03AE0000
194#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
195
196/*******************************************************************************
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]197 * Tegra Clock and Reset Controller constants
198 ******************************************************************************/
199#define TEGRA_CAR_RESET_BASE 0x05000000
200
201/*******************************************************************************
202 * Tegra micro-seconds timer constants
203 ******************************************************************************/
204#define TEGRA_TMRUS_BASE 0x0C2E0000
205
206/*******************************************************************************
207 * Tegra Power Mgmt Controller constants
208 ******************************************************************************/
209#define TEGRA_PMC_BASE 0x0C360000
210
211/*******************************************************************************
212 * Tegra scratch registers constants
213 ******************************************************************************/
214#define TEGRA_SCRATCH_BASE 0x0C390000
Varun Wadekar50402b12016-03-03 13:52:52 -0800[diff] [blame]215#define SECURE_SCRATCH_RSV6 0x680
216#define SECURE_SCRATCH_RSV11_LO 0x6A8
217#define SECURE_SCRATCH_RSV11_HI 0x6AC
Varun Wadekar48afb162016-05-23 11:47:34 -0700[diff] [blame]218#define SECURE_SCRATCH_RSV53_LO 0x7F8
219#define SECURE_SCRATCH_RSV53_HI 0x7FC
Harvey Hsieh719f3ec2016-07-29 20:10:59 +0800[diff] [blame]220#define SECURE_SCRATCH_RSV54_HI 0x804
221#define SECURE_SCRATCH_RSV55_LO 0x808
222#define SECURE_SCRATCH_RSV55_HI 0x80C
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]223
224/*******************************************************************************
225 * Tegra Memory Mapped Control Register Access Bus constants
226 ******************************************************************************/
227#define TEGRA_MMCRAB_BASE 0x0E000000
228
229/*******************************************************************************
230 * Tegra SMMU Controller constants
231 ******************************************************************************/
232#define TEGRA_SMMU_BASE 0x12000000
233
Varun Wadekard48c0c42015-12-30 15:15:08 -0800[diff] [blame]234/*******************************************************************************
235 * Tegra TZRAM constants
236 ******************************************************************************/
237#define TEGRA_TZRAM_BASE 0x30000000
Varun Wadekar2f583f82016-05-25 16:35:04 -0700[diff] [blame]238#define TEGRA_TZRAM_SIZE 0x40000
Varun Wadekard48c0c42015-12-30 15:15:08 -0800[diff] [blame]239
Varun Wadekar3cf31832015-08-25 17:03:14 +0530[diff] [blame]240#endif /* __TEGRA_DEF_H__ */