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review.trustedfirmware.org / TF-A / trusted-firmware-a / 109b91e38c8d4f73941c8574759560a1f1636d05 / . / plat / mediatek / mt8186 / include / platform_def.h
blob: c9d6f110f128436806a184577029ffefee12829e [file] [log] [blame]
Rex-BC Chen27132f12021-09-28 11:24:09 +0800[diff] [blame]1/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#define PLAT_PRIMARY_CPU 0x0
11
12#define MT_GIC_BASE (0x0C000000)
13#define MCUCFG_BASE (0x0C530000)
14#define IO_PHYS (0x10000000)
15
16/* Aggregate of all devices for MMU mapping */
17#define MTK_DEV_RNG0_BASE IO_PHYS
18#define MTK_DEV_RNG0_SIZE 0x400000
19#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
20#define MTK_DEV_RNG1_SIZE 0xa110000
21#define MTK_DEV_RNG2_BASE MT_GIC_BASE
22#define MTK_DEV_RNG2_SIZE 0x600000
23
24
25/*******************************************************************************
26 * UART related constants
27 ******************************************************************************/
28#define UART0_BASE (IO_PHYS + 0x01002000)
29
30#define UART_BAUDRATE 115200
31
32/*******************************************************************************
James Lo5bc88ec2021-10-06 18:12:30 +0800[diff] [blame]33 * PWRAP related constants
34 ******************************************************************************/
35#define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000)
36
37/*******************************************************************************
Penny Jan1b17e342021-10-03 10:11:04 +0800[diff] [blame]38 * EMI MPU related constants
39 ******************************************************************************/
40#define EMI_MPU_BASE (IO_PHYS + 0x0021B000)
41
42/*******************************************************************************
Christine Zhu206f1252021-10-11 21:29:58 +0800[diff] [blame]43 * GIC-600 & interrupt handling related constants
44 ******************************************************************************/
45/* Base MTK_platform compatible GIC memory map */
46#define BASE_GICD_BASE MT_GIC_BASE
47#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
48
Zhengnan Chen109b91e2021-10-12 17:05:49 +0800[diff] [blame^]49#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
50#define CIRQ_REG_NUM 11
51#define CIRQ_IRQ_NUM 326
52#define CIRQ_SPI_START 64
53#define MD_WDT_IRQ_BIT_ID 107
Christine Zhu206f1252021-10-11 21:29:58 +0800[diff] [blame]54/*******************************************************************************
Rex-BC Chen27132f12021-09-28 11:24:09 +0800[diff] [blame]55 * System counter frequency related constants
56 ******************************************************************************/
57#define SYS_COUNTER_FREQ_IN_TICKS 13000000
58#define SYS_COUNTER_FREQ_IN_MHZ 13
59
60/*******************************************************************************
61 * Platform binary types for linking
62 ******************************************************************************/
63#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
64#define PLATFORM_LINKER_ARCH aarch64
65
66/*******************************************************************************
67 * Generic platform constants
68 ******************************************************************************/
69#define PLATFORM_STACK_SIZE 0x800
70
71#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
72
73#define PLAT_MAX_PWR_LVL U(3)
74#define PLAT_MAX_RET_STATE U(1)
75#define PLAT_MAX_OFF_STATE U(9)
76
77#define PLATFORM_SYSTEM_COUNT U(1)
78#define PLATFORM_MCUSYS_COUNT U(1)
79#define PLATFORM_CLUSTER_COUNT U(1)
80#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
81#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
82
83#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
84#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
85
86#define SOC_CHIP_ID U(0x8186)
87
88/*******************************************************************************
89 * Platform memory map related constants
90 ******************************************************************************/
91#define TZRAM_BASE 0x54600000
92#define TZRAM_SIZE 0x00030000
93
94/*******************************************************************************
95 * BL31 specific defines.
96 ******************************************************************************/
97/*
98 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
99 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
100 * little space for growth.
101 */
102#define BL31_BASE (TZRAM_BASE + 0x1000)
103#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
104
105/*******************************************************************************
106 * Platform specific page table and MMU setup constants
107 ******************************************************************************/
108#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
109#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
110#define MAX_XLAT_TABLES 16
111#define MAX_MMAP_REGIONS 16
112
113/*******************************************************************************
114 * Declarations and constants to access the mailboxes safely. Each mailbox is
115 * aligned on the biggest cache line size in the platform. This is known only
116 * to the platform as it might have a combination of integrated and external
117 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
118 * line at any cache level. They could belong to different cpus/clusters &
119 * get written while being protected by different locks causing corruption of
120 * a valid mailbox address.
121 ******************************************************************************/
122#define CACHE_WRITEBACK_SHIFT 6
123#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
124#endif /* PLATFORM_DEF_H */