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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Louis Mayencourtf1be00d2020-01-24 13:30:28 +00002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Dan Handley97043ac2014-04-09 13:14:54 +01007#include <assert.h>
Antonio Nino Diaz40daecc2018-10-25 16:52:26 +01008#include <stdbool.h>
Andrew Thoelke167a9352014-06-04 21:10:52 +01009#include <string.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000010
11#include <platform_def.h>
12
13#include <arch.h>
14#include <arch_helpers.h>
Soby Mathewb7e398d2019-07-12 09:23:38 +010015#include <arch_features.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000016#include <bl31/interrupt_mgmt.h>
17#include <common/bl_common.h>
18#include <context.h>
19#include <lib/el3_runtime/context_mgmt.h>
20#include <lib/el3_runtime/pubsub_events.h>
21#include <lib/extensions/amu.h>
22#include <lib/extensions/mpam.h>
23#include <lib/extensions/spe.h>
24#include <lib/extensions/sve.h>
johpow016cac7242020-04-22 14:05:13 -050025#include <lib/extensions/twed.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000026#include <lib/utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000027
Achin Gupta7aea9082014-02-01 07:51:28 +000028
29/*******************************************************************************
30 * Context management library initialisation routine. This library is used by
31 * runtime services to share pointers to 'cpu_context' structures for the secure
32 * and non-secure states. Management of the structures and their associated
33 * memory is not done by the context management library e.g. the PSCI service
34 * manages the cpu context used for entry from and exit to the non-secure state.
35 * The Secure payload dispatcher service manages the context(s) corresponding to
36 * the secure state. It also uses this library to get access to the non-secure
37 * state cpu context pointers.
38 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
39 * which will used for programming an entry into a lower EL. The same context
40 * will used to save state upon exception entry from that EL.
41 ******************************************************************************/
Daniel Boulby87c85132018-09-20 14:12:46 +010042void __init cm_init(void)
Achin Gupta7aea9082014-02-01 07:51:28 +000043{
44 /*
45 * The context management library has only global data to intialize, but
46 * that will be done when the BSS is zeroed out
47 */
48}
49
50/*******************************************************************************
Soby Mathew12d0d002015-04-09 13:40:55 +010051 * The following function initializes the cpu_context 'ctx' for
Andrew Thoelke167a9352014-06-04 21:10:52 +010052 * first use, and sets the initial entrypoint state as specified by the
53 * entry_point_info structure.
54 *
55 * The security state to initialize is determined by the SECURE attribute
Antonio Nino Diaz1634cae2018-05-22 10:09:10 +010056 * of the entry_point_info.
Andrew Thoelke167a9352014-06-04 21:10:52 +010057 *
Paul Beesley8aabea32019-01-11 18:26:51 +000058 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathew12d0d002015-04-09 13:40:55 +010059 * timer availability for the new execution context.
Andrew Thoelke167a9352014-06-04 21:10:52 +010060 *
61 * To prepare the register state for entry call cm_prepare_el3_exit() and
62 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
63 * cm_e1_sysreg_context_restore().
64 ******************************************************************************/
Antonio Nino Diaz1634cae2018-05-22 10:09:10 +010065void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke167a9352014-06-04 21:10:52 +010066{
Soby Mathew12d0d002015-04-09 13:40:55 +010067 unsigned int security_state;
Louis Mayencourtf1be00d2020-01-24 13:30:28 +000068 u_register_t scr_el3;
Andrew Thoelke167a9352014-06-04 21:10:52 +010069 el3_state_t *state;
70 gp_regs_t *gp_regs;
Deepika Bhavnanieeb5a7b2019-09-03 21:08:51 +030071 u_register_t sctlr_elx, actlr_elx;
Andrew Thoelke167a9352014-06-04 21:10:52 +010072
Antonio Nino Diaza0fee742018-10-31 15:25:35 +000073 assert(ctx != NULL);
Andrew Thoelke167a9352014-06-04 21:10:52 +010074
Soby Mathew12d0d002015-04-09 13:40:55 +010075 security_state = GET_SECURITY_STATE(ep->h.attr);
76
Andrew Thoelke167a9352014-06-04 21:10:52 +010077 /* Clear any residual register values from the context */
Douglas Raillard32f0d3c2017-01-26 15:54:44 +000078 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke167a9352014-06-04 21:10:52 +010079
80 /*
David Cunado18f2efd2017-04-13 22:38:29 +010081 * SCR_EL3 was initialised during reset sequence in macro
82 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
83 * affect the next EL.
84 *
85 * The following fields are initially set to zero and then updated to
86 * the required value depending on the state of the SPSR_EL3 and the
87 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke167a9352014-06-04 21:10:52 +010088 */
Louis Mayencourtf1be00d2020-01-24 13:30:28 +000089 scr_el3 = read_scr();
Andrew Thoelke167a9352014-06-04 21:10:52 +010090 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
91 SCR_ST_BIT | SCR_HCE_BIT);
David Cunado18f2efd2017-04-13 22:38:29 +010092 /*
93 * SCR_NS: Set the security state of the next EL.
94 */
Andrew Thoelke167a9352014-06-04 21:10:52 +010095 if (security_state != SECURE)
96 scr_el3 |= SCR_NS_BIT;
David Cunado18f2efd2017-04-13 22:38:29 +010097 /*
98 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
99 * Exception level as specified by SPSR.
100 */
Andrew Thoelke167a9352014-06-04 21:10:52 +0100101 if (GET_RW(ep->spsr) == MODE_RW_64)
102 scr_el3 |= SCR_RW_BIT;
David Cunado18f2efd2017-04-13 22:38:29 +0100103 /*
104 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
105 * Secure timer registers to EL3, from AArch64 state only, if specified
106 * by the entrypoint attributes.
107 */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000108 if (EP_GET_ST(ep->h.attr) != 0U)
Andrew Thoelke167a9352014-06-04 21:10:52 +0100109 scr_el3 |= SCR_ST_BIT;
110
Julius Werner24f671f2018-08-28 14:45:43 -0700111#if !HANDLE_EA_EL3_FIRST
David Cunado18f2efd2017-04-13 22:38:29 +0100112 /*
113 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
114 * to EL3 when executing at a lower EL. When executing at EL3, External
115 * Aborts are taken to EL3.
116 */
Gerald Lejeuneadb4fcf2016-03-22 09:29:23 +0100117 scr_el3 &= ~SCR_EA_BIT;
118#endif
119
Jeenu Viswambharan1a7c1cf2017-12-08 12:13:51 +0000120#if FAULT_INJECTION_SUPPORT
121 /* Enable fault injection from lower ELs */
122 scr_el3 |= SCR_FIEN_BIT;
123#endif
124
Antonio Nino Diaz52839622019-01-31 11:58:00 +0000125#if !CTX_INCLUDE_PAUTH_REGS
126 /*
127 * If the pointer authentication registers aren't saved during world
128 * switches the value of the registers can be leaked from the Secure to
129 * the Non-secure world. To prevent this, rather than enabling pointer
130 * authentication everywhere, we only enable it in the Non-secure world.
131 *
132 * If the Secure world wants to use pointer authentication,
133 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
134 */
135 if (security_state == NON_SECURE)
136 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
137#endif /* !CTX_INCLUDE_PAUTH_REGS */
138
Soby Mathewb7e398d2019-07-12 09:23:38 +0100139 /*
Justin Chadwell9dd94382019-07-18 14:25:33 +0100140 * Enable MTE support. Support is enabled unilaterally for the normal
141 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
142 * set.
Soby Mathewb7e398d2019-07-12 09:23:38 +0100143 */
Justin Chadwell9dd94382019-07-18 14:25:33 +0100144#if CTX_INCLUDE_MTE_REGS
Justin Chadwell019b03a2019-09-20 09:13:14 +0100145 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
Justin Chadwell9dd94382019-07-18 14:25:33 +0100146 scr_el3 |= SCR_ATA_BIT;
147#else
Justin Chadwell019b03a2019-09-20 09:13:14 +0100148 unsigned int mte = get_armv8_5_mte_support();
Justin Chadwell9dd94382019-07-18 14:25:33 +0100149 if (mte == MTE_IMPLEMENTED_EL0) {
150 /*
151 * Can enable MTE across both worlds as no MTE registers are
152 * used
153 */
154 scr_el3 |= SCR_ATA_BIT;
155 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
156 /*
157 * Can only enable MTE in Non-Secure world without register
158 * saving
159 */
160 scr_el3 |= SCR_ATA_BIT;
Soby Mathewb7e398d2019-07-12 09:23:38 +0100161 }
Justin Chadwell9dd94382019-07-18 14:25:33 +0100162#endif
Soby Mathewb7e398d2019-07-12 09:23:38 +0100163
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900164#ifdef IMAGE_BL31
Yatharth Kocharbbf8f6f2015-10-02 17:56:48 +0100165 /*
Paul Beesley8aabea32019-01-11 18:26:51 +0000166 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
David Cunado18f2efd2017-04-13 22:38:29 +0100167 * indicated by the interrupt routing model for BL31.
Yatharth Kocharbbf8f6f2015-10-02 17:56:48 +0100168 */
Andrew Thoelke167a9352014-06-04 21:10:52 +0100169 scr_el3 |= get_scr_el3_from_routing_model(security_state);
Yatharth Kocharbbf8f6f2015-10-02 17:56:48 +0100170#endif
Andrew Thoelke167a9352014-06-04 21:10:52 +0100171
172 /*
David Cunado18f2efd2017-04-13 22:38:29 +0100173 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
174 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
175 * next mode is Hyp.
Jimmy Brisson110ee432020-04-16 10:47:56 -0500176 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
177 * same conditions as HVC instructions and when the processor supports
178 * ARMv8.6-FGT.
Andrew Thoelke167a9352014-06-04 21:10:52 +0100179 */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000180 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
181 || ((GET_RW(ep->spsr) != MODE_RW_64)
182 && (GET_M32(ep->spsr) == MODE32_hyp))) {
Andrew Thoelke167a9352014-06-04 21:10:52 +0100183 scr_el3 |= SCR_HCE_BIT;
Jimmy Brisson110ee432020-04-16 10:47:56 -0500184
185 if (is_armv8_6_fgt_present()) {
186 scr_el3 |= SCR_FGTEN_BIT;
187 }
Andrew Thoelke167a9352014-06-04 21:10:52 +0100188 }
189
Achin Gupta0376e7c2019-10-11 14:44:05 +0100190 /* Enable S-EL2 if the next EL is EL2 and security state is secure */
Artsem Artsemenkadb3ae852019-11-26 16:40:31 +0000191 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
192 if (GET_RW(ep->spsr) != MODE_RW_64) {
193 ERROR("S-EL2 can not be used in AArch32.");
194 panic();
195 }
196
Achin Gupta0376e7c2019-10-11 14:44:05 +0100197 scr_el3 |= SCR_EEL2_BIT;
Artsem Artsemenkadb3ae852019-11-26 16:40:31 +0000198 }
Achin Gupta0376e7c2019-10-11 14:44:05 +0100199
David Cunado18f2efd2017-04-13 22:38:29 +0100200 /*
201 * Initialise SCTLR_EL1 to the reset value corresponding to the target
202 * execution state setting all fields rather than relying of the hw.
203 * Some fields have architecturally UNKNOWN reset values and these are
204 * set to zero.
205 *
206 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
207 *
208 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
209 * required by PSCI specification)
210 */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000211 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
David Cunado18f2efd2017-04-13 22:38:29 +0100212 if (GET_RW(ep->spsr) == MODE_RW_64)
213 sctlr_elx |= SCTLR_EL1_RES1;
214 else {
215 /*
216 * If the target execution state is AArch32 then the following
217 * fields need to be set.
218 *
219 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
220 * instructions are not trapped to EL1.
221 *
222 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
223 * instructions are not trapped to EL1.
224 *
225 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
226 * CP15DMB, CP15DSB, and CP15ISB instructions.
227 */
228 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
229 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
230 }
231
Louis Mayencourt5f5d1ed2019-02-20 12:11:41 +0000232#if ERRATA_A75_764081
233 /*
234 * If workaround of errata 764081 for Cortex-A75 is used then set
235 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
236 */
237 sctlr_elx |= SCTLR_IESB_BIT;
238#endif
239
johpow016cac7242020-04-22 14:05:13 -0500240 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
241 if (is_armv8_6_twed_present()) {
242 uint32_t delay = plat_arm_set_twedel_scr_el3();
243
244 if (delay != TWED_DISABLED) {
245 /* Make sure delay value fits */
246 assert((delay & ~SCR_TWEDEL_MASK) == 0U);
247
248 /* Set delay in SCR_EL3 */
249 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
250 scr_el3 |= ((delay & SCR_TWEDEL_MASK)
251 << SCR_TWEDEL_SHIFT);
252
253 /* Enable WFE delay */
254 scr_el3 |= SCR_TWEDEn_BIT;
255 }
256 }
257
David Cunado18f2efd2017-04-13 22:38:29 +0100258 /*
259 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
Paul Beesley8aabea32019-01-11 18:26:51 +0000260 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
David Cunado18f2efd2017-04-13 22:38:29 +0100261 * are not part of the stored cpu_context.
262 */
Max Shvetsov28259462020-02-17 16:15:47 +0000263 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
David Cunado18f2efd2017-04-13 22:38:29 +0100264
Varun Wadekar2ab96172018-05-08 10:52:36 -0700265 /*
266 * Base the context ACTLR_EL1 on the current value, as it is
267 * implementation defined. The context restore process will write
268 * the value from the context to the actual register and can cause
269 * problems for processor cores that don't expect certain bits to
270 * be zero.
271 */
272 actlr_elx = read_actlr_el1();
Max Shvetsov28259462020-02-17 16:15:47 +0000273 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
Varun Wadekar2ab96172018-05-08 10:52:36 -0700274
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100275 /*
276 * Populate EL3 state so that we've the right context
277 * before doing ERET
278 */
Andrew Thoelke167a9352014-06-04 21:10:52 +0100279 state = get_el3state_ctx(ctx);
280 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
281 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
282 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
283
284 /*
285 * Store the X0-X7 value from the entrypoint into the context
286 * Use memcpy as we are in control of the layout of the structures
287 */
288 gp_regs = get_gpregs_ctx(ctx);
289 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
290}
291
292/*******************************************************************************
Dimitris Papastamos0fd0f222017-11-07 09:55:29 +0000293 * Enable architecture extensions on first entry to Non-secure world.
294 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
295 * it is zero.
296 ******************************************************************************/
Antonio Nino Diaz40daecc2018-10-25 16:52:26 +0100297static void enable_extensions_nonsecure(bool el2_unused)
Dimitris Papastamos0fd0f222017-11-07 09:55:29 +0000298{
299#if IMAGE_BL31
Dimitris Papastamos281a08c2017-10-13 12:06:06 +0100300#if ENABLE_SPE_FOR_LOWER_ELS
301 spe_enable(el2_unused);
302#endif
Dimitris Papastamos380559c2017-10-12 13:02:29 +0100303
304#if ENABLE_AMU
305 amu_enable(el2_unused);
306#endif
David Cunado1a853372017-10-20 11:30:57 +0100307
308#if ENABLE_SVE_FOR_NS
309 sve_enable(el2_unused);
310#endif
Jeenu Viswambharan5f835912018-07-31 16:13:33 +0100311
312#if ENABLE_MPAM_FOR_LOWER_ELS
313 mpam_enable(el2_unused);
314#endif
Dimitris Papastamos0fd0f222017-11-07 09:55:29 +0000315#endif
316}
317
318/*******************************************************************************
Soby Mathew12d0d002015-04-09 13:40:55 +0100319 * The following function initializes the cpu_context for a CPU specified by
320 * its `cpu_idx` for first use, and sets the initial entrypoint state as
321 * specified by the entry_point_info structure.
322 ******************************************************************************/
323void cm_init_context_by_index(unsigned int cpu_idx,
324 const entry_point_info_t *ep)
325{
326 cpu_context_t *ctx;
327 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz1634cae2018-05-22 10:09:10 +0100328 cm_setup_context(ctx, ep);
Soby Mathew12d0d002015-04-09 13:40:55 +0100329}
330
331/*******************************************************************************
332 * The following function initializes the cpu_context for the current CPU
333 * for first use, and sets the initial entrypoint state as specified by the
334 * entry_point_info structure.
335 ******************************************************************************/
336void cm_init_my_context(const entry_point_info_t *ep)
337{
338 cpu_context_t *ctx;
339 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz1634cae2018-05-22 10:09:10 +0100340 cm_setup_context(ctx, ep);
Soby Mathew12d0d002015-04-09 13:40:55 +0100341}
342
343/*******************************************************************************
Andrew Thoelke167a9352014-06-04 21:10:52 +0100344 * Prepare the CPU system registers for first entry into secure or normal world
345 *
346 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
347 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
348 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
349 * For all entries, the EL1 registers are initialized from the cpu_context
350 ******************************************************************************/
351void cm_prepare_el3_exit(uint32_t security_state)
352{
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000353 u_register_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke167a9352014-06-04 21:10:52 +0100354 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz40daecc2018-10-25 16:52:26 +0100355 bool el2_unused = false;
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000356 uint64_t hcr_el2 = 0U;
Andrew Thoelke167a9352014-06-04 21:10:52 +0100357
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000358 assert(ctx != NULL);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100359
360 if (security_state == NON_SECURE) {
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000361 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000362 CTX_SCR_EL3);
363 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke167a9352014-06-04 21:10:52 +0100364 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Max Shvetsov28259462020-02-17 16:15:47 +0000365 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000366 CTX_SCTLR_EL1);
Ken Kuang2e09d4f2017-08-23 16:03:29 +0800367 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke167a9352014-06-04 21:10:52 +0100368 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt5f5d1ed2019-02-20 12:11:41 +0000369#if ERRATA_A75_764081
370 /*
371 * If workaround of errata 764081 for Cortex-A75 is used
372 * then set SCTLR_EL2.IESB to enable Implicit Error
373 * Synchronization Barrier.
374 */
375 sctlr_elx |= SCTLR_IESB_BIT;
376#endif
Andrew Thoelke167a9352014-06-04 21:10:52 +0100377 write_sctlr_el2(sctlr_elx);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000378 } else if (el_implemented(2) != EL_IMPL_NONE) {
Antonio Nino Diaz40daecc2018-10-25 16:52:26 +0100379 el2_unused = true;
Dimitris Papastamos0fd0f222017-11-07 09:55:29 +0000380
David Cunado18f2efd2017-04-13 22:38:29 +0100381 /*
382 * EL2 present but unused, need to disable safely.
383 * SCTLR_EL2 can be ignored in this case.
384 *
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +0100385 * Set EL2 register width appropriately: Set HCR_EL2
386 * field to match SCR_EL3.RW.
David Cunado18f2efd2017-04-13 22:38:29 +0100387 */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000388 if ((scr_el3 & SCR_RW_BIT) != 0U)
Jeenu Viswambharan3ff4aaa2018-08-15 14:29:29 +0100389 hcr_el2 |= HCR_RW_BIT;
390
391 /*
392 * For Armv8.3 pointer authentication feature, disable
393 * traps to EL2 when accessing key registers or using
394 * pointer authentication instructions from lower ELs.
395 */
396 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
397
398 write_hcr_el2(hcr_el2);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100399
David Cunado18f2efd2017-04-13 22:38:29 +0100400 /*
401 * Initialise CPTR_EL2 setting all fields rather than
402 * relying on the hw. All fields have architecturally
403 * UNKNOWN reset values.
404 *
405 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
406 * accesses to the CPACR_EL1 or CPACR from both
407 * Execution states do not trap to EL2.
408 *
409 * CPTR_EL2.TTA: Set to zero so that Non-secure System
410 * register accesses to the trace registers from both
411 * Execution states do not trap to EL2.
412 *
413 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
414 * to SIMD and floating-point functionality from both
415 * Execution states do not trap to EL2.
416 */
417 write_cptr_el2(CPTR_EL2_RESET_VAL &
418 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
419 | CPTR_EL2_TFP_BIT));
Andrew Thoelke167a9352014-06-04 21:10:52 +0100420
David Cunado18f2efd2017-04-13 22:38:29 +0100421 /*
Paul Beesley8aabea32019-01-11 18:26:51 +0000422 * Initialise CNTHCTL_EL2. All fields are
David Cunado18f2efd2017-04-13 22:38:29 +0100423 * architecturally UNKNOWN on reset and are set to zero
424 * except for field(s) listed below.
425 *
426 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
427 * Hyp mode of Non-secure EL0 and EL1 accesses to the
428 * physical timer registers.
429 *
430 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
431 * Hyp mode of Non-secure EL0 and EL1 accesses to the
432 * physical counter registers.
433 */
434 write_cnthctl_el2(CNTHCTL_RESET_VAL |
435 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100436
David Cunado18f2efd2017-04-13 22:38:29 +0100437 /*
438 * Initialise CNTVOFF_EL2 to zero as it resets to an
439 * architecturally UNKNOWN value.
440 */
Soby Mathew14c05262014-08-29 14:41:58 +0100441 write_cntvoff_el2(0);
442
David Cunado18f2efd2017-04-13 22:38:29 +0100443 /*
444 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
445 * MPIDR_EL1 respectively.
446 */
Andrew Thoelke167a9352014-06-04 21:10:52 +0100447 write_vpidr_el2(read_midr_el1());
448 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux85d80e52015-11-25 17:00:44 +0000449
450 /*
David Cunado18f2efd2017-04-13 22:38:29 +0100451 * Initialise VTTBR_EL2. All fields are architecturally
452 * UNKNOWN on reset.
453 *
454 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
455 * 2 address translation is disabled, cache maintenance
456 * operations depend on the VMID.
457 *
458 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
459 * translation is disabled.
Sandrine Bailleux85d80e52015-11-25 17:00:44 +0000460 */
David Cunado18f2efd2017-04-13 22:38:29 +0100461 write_vttbr_el2(VTTBR_RESET_VAL &
462 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
463 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
464
David Cunado495f3d32016-10-31 17:37:34 +0000465 /*
David Cunado18f2efd2017-04-13 22:38:29 +0100466 * Initialise MDCR_EL2, setting all fields rather than
467 * relying on hw. Some fields are architecturally
468 * UNKNOWN on reset.
469 *
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100470 * MDCR_EL2.HLP: Set to one so that event counter
471 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
472 * occurs on the increment that changes
473 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
474 * implemented. This bit is RES0 in versions of the
475 * architecture earlier than ARMv8.5, setting it to 1
476 * doesn't have any effect on them.
477 *
478 * MDCR_EL2.TTRF: Set to zero so that access to Trace
479 * Filter Control register TRFCR_EL1 at EL1 is not
480 * trapped to EL2. This bit is RES0 in versions of
481 * the architecture earlier than ARMv8.4.
482 *
483 * MDCR_EL2.HPMD: Set to one so that event counting is
484 * prohibited at EL2. This bit is RES0 in versions of
485 * the architecture earlier than ARMv8.1, setting it
486 * to 1 doesn't have any effect on them.
487 *
488 * MDCR_EL2.TPMS: Set to zero so that accesses to
489 * Statistical Profiling control registers from EL1
490 * do not trap to EL2. This bit is RES0 when SPE is
491 * not implemented.
492 *
David Cunado18f2efd2017-04-13 22:38:29 +0100493 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
494 * EL1 System register accesses to the Debug ROM
495 * registers are not trapped to EL2.
496 *
497 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
498 * System register accesses to the powerdown debug
499 * registers are not trapped to EL2.
500 *
501 * MDCR_EL2.TDA: Set to zero so that System register
502 * accesses to the debug registers do not trap to EL2.
503 *
504 * MDCR_EL2.TDE: Set to zero so that debug exceptions
505 * are not routed to EL2.
506 *
507 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
508 * Monitors.
509 *
510 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
511 * EL1 accesses to all Performance Monitors registers
512 * are not trapped to EL2.
513 *
514 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
515 * and EL1 accesses to the PMCR_EL0 or PMCR are not
516 * trapped to EL2.
517 *
518 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
519 * architecturally-defined reset value.
David Cunado495f3d32016-10-31 17:37:34 +0000520 */
Alexei Fedorove290a8fc2019-08-13 15:17:53 +0100521 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
522 MDCR_EL2_HPMD) |
523 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
524 >> PMCR_EL0_N_SHIFT)) &
525 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
526 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
527 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
528 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
529 MDCR_EL2_TPMCR_BIT);
dp-armd832aee2017-05-23 09:32:49 +0100530
dp-armd832aee2017-05-23 09:32:49 +0100531 write_mdcr_el2(mdcr_el2);
532
David Cunado939f66d2016-11-25 00:21:59 +0000533 /*
David Cunado18f2efd2017-04-13 22:38:29 +0100534 * Initialise HSTR_EL2. All fields are architecturally
535 * UNKNOWN on reset.
536 *
537 * HSTR_EL2.T<n>: Set all these fields to zero so that
538 * Non-secure EL0 or EL1 accesses to System registers
539 * do not trap to EL2.
David Cunado939f66d2016-11-25 00:21:59 +0000540 */
David Cunado18f2efd2017-04-13 22:38:29 +0100541 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunado939f66d2016-11-25 00:21:59 +0000542 /*
David Cunado18f2efd2017-04-13 22:38:29 +0100543 * Initialise CNTHP_CTL_EL2. All fields are
544 * architecturally UNKNOWN on reset.
545 *
546 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
547 * physical timer and prevent timer interrupts.
David Cunado939f66d2016-11-25 00:21:59 +0000548 */
David Cunado18f2efd2017-04-13 22:38:29 +0100549 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
550 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke167a9352014-06-04 21:10:52 +0100551 }
Dimitris Papastamos0fd0f222017-11-07 09:55:29 +0000552 enable_extensions_nonsecure(el2_unused);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100553 }
554
Dimitris Papastamos17b4c0d2017-10-13 15:27:58 +0100555 cm_el1_sysregs_context_restore(security_state);
556 cm_set_next_eret_context(security_state);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100557}
558
Max Shvetsov28f39f02020-02-25 13:56:19 +0000559#if CTX_INCLUDE_EL2_REGS
560/*******************************************************************************
561 * Save EL2 sysreg context
562 ******************************************************************************/
563void cm_el2_sysregs_context_save(uint32_t security_state)
564{
565 u_register_t scr_el3 = read_scr();
566
567 /*
568 * Always save the non-secure EL2 context, only save the
569 * S-EL2 context if S-EL2 is enabled.
570 */
571 if ((security_state == NON_SECURE) ||
572 ((scr_el3 & SCR_EEL2_BIT) != 0U)) {
573 cpu_context_t *ctx;
574
575 ctx = cm_get_context(security_state);
576 assert(ctx != NULL);
577
Max Shvetsov28259462020-02-17 16:15:47 +0000578 el2_sysregs_context_save(get_el2_sysregs_ctx(ctx));
Max Shvetsov28f39f02020-02-25 13:56:19 +0000579 }
580}
581
582/*******************************************************************************
583 * Restore EL2 sysreg context
584 ******************************************************************************/
585void cm_el2_sysregs_context_restore(uint32_t security_state)
586{
587 u_register_t scr_el3 = read_scr();
588
589 /*
590 * Always restore the non-secure EL2 context, only restore the
591 * S-EL2 context if S-EL2 is enabled.
592 */
593 if ((security_state == NON_SECURE) ||
594 ((scr_el3 & SCR_EEL2_BIT) != 0U)) {
595 cpu_context_t *ctx;
596
597 ctx = cm_get_context(security_state);
598 assert(ctx != NULL);
599
Max Shvetsov28259462020-02-17 16:15:47 +0000600 el2_sysregs_context_restore(get_el2_sysregs_ctx(ctx));
Max Shvetsov28f39f02020-02-25 13:56:19 +0000601 }
602}
603#endif /* CTX_INCLUDE_EL2_REGS */
604
Andrew Thoelke167a9352014-06-04 21:10:52 +0100605/*******************************************************************************
Soby Mathewfdfabec2014-07-04 16:02:26 +0100606 * The next four functions are used by runtime services to save and restore
607 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000608 * state.
609 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000610void cm_el1_sysregs_context_save(uint32_t security_state)
611{
Dan Handleyfb037bf2014-04-10 15:37:22 +0100612 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000613
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100614 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000615 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000616
Max Shvetsov28259462020-02-17 16:15:47 +0000617 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
Dimitris Papastamos17b4c0d2017-10-13 15:27:58 +0100618
619#if IMAGE_BL31
620 if (security_state == SECURE)
621 PUBLISH_EVENT(cm_exited_secure_world);
622 else
623 PUBLISH_EVENT(cm_exited_normal_world);
624#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000625}
626
627void cm_el1_sysregs_context_restore(uint32_t security_state)
628{
Dan Handleyfb037bf2014-04-10 15:37:22 +0100629 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000630
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100631 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000632 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000633
Max Shvetsov28259462020-02-17 16:15:47 +0000634 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
Dimitris Papastamos17b4c0d2017-10-13 15:27:58 +0100635
636#if IMAGE_BL31
637 if (security_state == SECURE)
638 PUBLISH_EVENT(cm_entering_secure_world);
639 else
640 PUBLISH_EVENT(cm_entering_normal_world);
641#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000642}
643
644/*******************************************************************************
Achin Guptac429b5e2014-05-04 18:38:28 +0100645 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
646 * given security state with the given entrypoint
Achin Gupta607084e2014-02-09 18:24:19 +0000647 ******************************************************************************/
Soby Mathew4c0d0392016-06-16 14:52:04 +0100648void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Achin Gupta607084e2014-02-09 18:24:19 +0000649{
Dan Handleyfb037bf2014-04-10 15:37:22 +0100650 cpu_context_t *ctx;
651 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000652
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100653 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000654 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +0000655
656 /* Populate EL3 state so that ERET jumps to the correct entry */
657 state = get_el3state_ctx(ctx);
658 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
659}
660
661/*******************************************************************************
Andrew Thoelke167a9352014-06-04 21:10:52 +0100662 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
663 * pertaining to the given security state
664 ******************************************************************************/
665void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathew4c0d0392016-06-16 14:52:04 +0100666 uintptr_t entrypoint, uint32_t spsr)
Andrew Thoelke167a9352014-06-04 21:10:52 +0100667{
668 cpu_context_t *ctx;
669 el3_state_t *state;
670
671 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000672 assert(ctx != NULL);
Andrew Thoelke167a9352014-06-04 21:10:52 +0100673
674 /* Populate EL3 state so that ERET jumps to the correct entry */
675 state = get_el3state_ctx(ctx);
676 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
677 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
678}
679
680/*******************************************************************************
Achin Guptac429b5e2014-05-04 18:38:28 +0100681 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
682 * pertaining to the given security state using the value and bit position
683 * specified in the parameters. It preserves all other bits.
684 ******************************************************************************/
685void cm_write_scr_el3_bit(uint32_t security_state,
686 uint32_t bit_pos,
687 uint32_t value)
688{
689 cpu_context_t *ctx;
690 el3_state_t *state;
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000691 u_register_t scr_el3;
Achin Guptac429b5e2014-05-04 18:38:28 +0100692
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100693 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000694 assert(ctx != NULL);
Achin Guptac429b5e2014-05-04 18:38:28 +0100695
696 /* Ensure that the bit position is a valid one */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000697 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Guptac429b5e2014-05-04 18:38:28 +0100698
699 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000700 assert(value <= 1U);
Achin Guptac429b5e2014-05-04 18:38:28 +0100701
702 /*
703 * Get the SCR_EL3 value from the cpu context, clear the desired bit
704 * and set it to its new value.
705 */
706 state = get_el3state_ctx(ctx);
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000707 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000708 scr_el3 &= ~(1U << bit_pos);
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000709 scr_el3 |= (u_register_t)value << bit_pos;
Achin Guptac429b5e2014-05-04 18:38:28 +0100710 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
711}
712
713/*******************************************************************************
714 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
715 * given security state.
716 ******************************************************************************/
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000717u_register_t cm_get_scr_el3(uint32_t security_state)
Achin Guptac429b5e2014-05-04 18:38:28 +0100718{
719 cpu_context_t *ctx;
720 el3_state_t *state;
721
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100722 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000723 assert(ctx != NULL);
Achin Guptac429b5e2014-05-04 18:38:28 +0100724
725 /* Populate EL3 state so that ERET jumps to the correct entry */
726 state = get_el3state_ctx(ctx);
Louis Mayencourtf1be00d2020-01-24 13:30:28 +0000727 return read_ctx_reg(state, CTX_SCR_EL3);
Achin Guptac429b5e2014-05-04 18:38:28 +0100728}
729
730/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000731 * This function is used to program the context that's used for exception
732 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
733 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000734 ******************************************************************************/
735void cm_set_next_eret_context(uint32_t security_state)
736{
Dan Handleyfb037bf2014-04-10 15:37:22 +0100737 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000738
Andrew Thoelke08ab89d2014-05-14 17:09:32 +0100739 ctx = cm_get_context(security_state);
Antonio Nino Diaza0fee742018-10-31 15:25:35 +0000740 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000741
Andrew Thoelke167a9352014-06-04 21:10:52 +0100742 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000743}