blob: a8c558b67477ff652cc5b42c90793399978e025d [file] [log] [blame]
Dan Handleyb4315302015-03-19 18:58:55 +00001/*
2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <asm_macros.S>
32#include <cpu_macros.S>
33#include <css_def.h>
34
35 .weak plat_secondary_cold_boot_setup
Soby Mathew38dce702015-07-01 16:16:20 +010036 .weak plat_get_my_entrypoint
Dan Handleyb4315302015-03-19 18:58:55 +000037 .weak platform_mem_init
Soby Mathew38dce702015-07-01 16:16:20 +010038 .globl plat_arm_calc_core_pos
39 .weak plat_is_my_cpu_primary
Dan Handleyb4315302015-03-19 18:58:55 +000040
41 /* -----------------------------------------------------
42 * void plat_secondary_cold_boot_setup (void);
43 *
44 * This function performs any platform specific actions
45 * needed for a secondary cpu after a cold reset e.g
46 * mark the cpu's presence, mechanism to place it in a
47 * holding pen etc.
48 * -----------------------------------------------------
49 */
50func plat_secondary_cold_boot_setup
51 /* todo: Implement secondary CPU cold boot setup on CSS platforms */
52cb_panic:
53 b cb_panic
54endfunc plat_secondary_cold_boot_setup
55
56 /* -----------------------------------------------------
Soby Mathew38dce702015-07-01 16:16:20 +010057 * unsigned long plat_get_my_entrypoint (void);
Dan Handleyb4315302015-03-19 18:58:55 +000058 *
59 * Main job of this routine is to distinguish between
Soby Mathew38dce702015-07-01 16:16:20 +010060 * a cold and warm boot on the current CPU.
Dan Handleyb4315302015-03-19 18:58:55 +000061 * On a cold boot the secondaries first wait for the
62 * platform to be initialized after which they are
63 * hotplugged in. The primary proceeds to perform the
64 * platform initialization.
65 * On a warm boot, each cpu jumps to the address in its
66 * mailbox.
67 *
68 * TODO: Not a good idea to save lr in a temp reg
69 * -----------------------------------------------------
70 */
Soby Mathew38dce702015-07-01 16:16:20 +010071func plat_get_my_entrypoint
Dan Handleyb4315302015-03-19 18:58:55 +000072 mov x9, x30 // lr
Soby Mathew38dce702015-07-01 16:16:20 +010073 bl plat_my_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +000074 ldr x1, =TRUSTED_MAILBOXES_BASE
75 lsl x0, x0, #TRUSTED_MAILBOX_SHIFT
76 ldr x0, [x1, x0]
77 ret x9
Soby Mathew38dce702015-07-01 16:16:20 +010078endfunc plat_get_my_entrypoint
Dan Handleyb4315302015-03-19 18:58:55 +000079
Soby Mathew38dce702015-07-01 16:16:20 +010080 /* -----------------------------------------------------------
81 * unsigned int plat_arm_calc_core_pos(uint64_t mpidr)
82 * Function to calculate the core position by
83 * swapping the cluster order. This is necessary in order to
84 * match the format of the boot information passed by the SCP
85 * and read in platform_is_primary_cpu below.
86 * -----------------------------------------------------------
Dan Handleyb4315302015-03-19 18:58:55 +000087 */
Soby Mathew38dce702015-07-01 16:16:20 +010088func plat_arm_calc_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +000089 and x1, x0, #MPIDR_CPU_MASK
90 and x0, x0, #MPIDR_CLUSTER_MASK
91 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
92 add x0, x1, x0, LSR #6
93 ret
Soby Mathew38dce702015-07-01 16:16:20 +010094endfunc plat_arm_calc_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +000095
96 /* -----------------------------------------------------
97 * void platform_mem_init(void);
98 *
99 * We don't need to carry out any memory initialization
100 * on CSS platforms. The Secure RAM is accessible straight away.
101 * -----------------------------------------------------
102 */
103func platform_mem_init
104 ret
105endfunc platform_mem_init
106
107 /* -----------------------------------------------------
Soby Mathew38dce702015-07-01 16:16:20 +0100108 * unsigned int plat_is_my_cpu_primary (void);
Dan Handleyb4315302015-03-19 18:58:55 +0000109 *
Soby Mathew38dce702015-07-01 16:16:20 +0100110 * Find out whether the current cpu is the primary
Dan Handleyb4315302015-03-19 18:58:55 +0000111 * cpu (applicable ony after a cold boot)
112 * -----------------------------------------------------
113 */
Soby Mathew38dce702015-07-01 16:16:20 +0100114func plat_is_my_cpu_primary
Dan Handleyb4315302015-03-19 18:58:55 +0000115 mov x9, x30
Soby Mathew38dce702015-07-01 16:16:20 +0100116 bl plat_my_core_pos
Dan Handleyb4315302015-03-19 18:58:55 +0000117 ldr x1, =SCP_BOOT_CFG_ADDR
118 ldr x1, [x1]
Soby Mathew19af6fc2015-05-26 16:58:54 +0100119 ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_BIT_WIDTH
Dan Handleyb4315302015-03-19 18:58:55 +0000120 cmp x0, x1
121 cset x0, eq
122 ret x9
Soby Mathew38dce702015-07-01 16:16:20 +0100123endfunc plat_is_my_cpu_primary