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review.trustedfirmware.org / TF-A / trusted-firmware-a / 3eb2d672fcd2d86ba56359760d2eb0df758a6843 / . / plat / arm / board / common / board_css_common.c
blob: 2495e28fee8bdb133e14841a5f05ee3239ec8ee0 [file] [log] [blame]
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]1/*
Summer Qin54661cd2017-04-24 16:49:28 +0100[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-arm82cb2c12017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]5 */
6#include <arm_def.h>
7#include <plat_arm.h>
8
9/*
Sandrine Bailleuxb5fa6562016-05-18 16:11:47 +0100[diff] [blame]10 * Table of memory regions for different BL stages to map using the MMU.
11 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
12 * takes care of mapping it.
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]13 */
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]14#ifdef IMAGE_BL1
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]15const mmap_region_t plat_arm_mmap[] = {
16 ARM_MAP_SHARED_RAM,
Juan Castillo7b4c1402015-10-06 14:01:35 +0100[diff] [blame]17 V2M_MAP_FLASH0_RO,
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]18 V2M_MAP_IOFPGA,
19 CSS_MAP_DEVICE,
20 SOC_CSS_MAP_DEVICE,
Yatharth Kochar436223d2015-10-11 14:14:55 +0100[diff] [blame]21#if TRUSTED_BOARD_BOOT
Sandrine Bailleux284c3d62017-05-26 15:48:10 +0100[diff] [blame]22 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar436223d2015-10-11 14:14:55 +0100[diff] [blame]23 ARM_MAP_NS_DRAM1,
24#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]25 {0}
26};
27#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]28#ifdef IMAGE_BL2
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]29const mmap_region_t plat_arm_mmap[] = {
30 ARM_MAP_SHARED_RAM,
Juan Castillo7b4c1402015-10-06 14:01:35 +0100[diff] [blame]31 V2M_MAP_FLASH0_RO,
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]32 V2M_MAP_IOFPGA,
33 CSS_MAP_DEVICE,
34 SOC_CSS_MAP_DEVICE,
35 ARM_MAP_NS_DRAM1,
Sandrine Bailleux3eb2d672017-08-30 10:59:22 +0100[diff] [blame^]36#ifdef SPD_tspd
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]37 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleux3eb2d672017-08-30 10:59:22 +0100[diff] [blame^]38#endif
Summer Qin54661cd2017-04-24 16:49:28 +0100[diff] [blame]39#ifdef SPD_opteed
40 ARM_OPTEE_PAGEABLE_LOAD_MEM,
41#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]42 {0}
43};
44#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]45#ifdef IMAGE_BL2U
Yatharth Kochardcda29f2015-10-14 15:28:11 +0100[diff] [blame]46const mmap_region_t plat_arm_mmap[] = {
47 ARM_MAP_SHARED_RAM,
48 CSS_MAP_DEVICE,
49 SOC_CSS_MAP_DEVICE,
50 {0}
51};
52#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]53#ifdef IMAGE_BL31
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]54const mmap_region_t plat_arm_mmap[] = {
55 ARM_MAP_SHARED_RAM,
56 V2M_MAP_IOFPGA,
57 CSS_MAP_DEVICE,
Soby Mathew40111d442016-11-14 12:44:32 +0000[diff] [blame]58#if CSS_USE_SCMI_DRIVER
59 /*
60 * The SCMI payload area is currently in the Non Secure SRAM. This is
61 * a potential security risk but this will be resolved once SCP
62 * completely replaces SCPI with SCMI as the only communication
63 * protocol.
64 */
65 CSS_MAP_NSRAM,
66#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]67 SOC_CSS_MAP_DEVICE,
68 {0}
69};
70#endif
Masahiro Yamada3d8256b2016-12-25 23:36:24 +0900[diff] [blame]71#ifdef IMAGE_BL32
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]72const mmap_region_t plat_arm_mmap[] = {
Yatharth Kochar6f249342016-11-14 12:00:41 +0000[diff] [blame]73#ifdef AARCH32
74 ARM_MAP_SHARED_RAM,
75#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000[diff] [blame]76 V2M_MAP_IOFPGA,
77 CSS_MAP_DEVICE,
78 SOC_CSS_MAP_DEVICE,
79 {0}
80};
81#endif
82
83ARM_CASSERT_MMAP