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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke0a30cf52014-03-18 13:46:55 +000032#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033
Jeenu Viswambharan9f98aa12014-03-11 11:06:45 +000034 .globl bl1_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010035
36
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 /* -----------------------------------------------------
Jeenu Viswambharan9f98aa12014-03-11 11:06:45 +000038 * bl1_entrypoint() is the entry point into the trusted
Achin Gupta4f6ad662013-10-25 09:08:21 +010039 * firmware code when a cpu is released from warm or
40 * cold reset.
41 * -----------------------------------------------------
42 */
43
Andrew Thoelke0a30cf52014-03-18 13:46:55 +000044func bl1_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 /* ---------------------------------------------
Andrew Thoelke40fd0722014-04-24 15:33:24 +010046 * Set the CPU endianness before doing anything
47 * that might involve memory reads or writes
48 * ---------------------------------------------
49 */
50 mrs x0, sctlr_el3
51 bic x0, x0, #SCTLR_EE_BIT
52 msr sctlr_el3, x0
53 isb
54
55 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 * Perform any processor specific actions upon
57 * reset e.g. cache, tlb invalidations etc.
58 * ---------------------------------------------
59 */
60 bl cpu_reset_handler
61
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000062 /* ---------------------------------------------
63 * Set the exception vector to something sane.
64 * ---------------------------------------------
65 */
Sandrine Bailleux6c595b32014-03-24 10:24:08 +000066 adr x0, bl1_exceptions
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000067 msr vbar_el3, x0
68
Harry Liebel4f603682014-01-14 18:11:48 +000069 /* ---------------------------------------------------------------------
70 * The initial state of the Architectural feature trap register
71 * (CPTR_EL3) is unknown and it must be set to a known state. All
72 * feature traps are disabled. Some bits in this register are marked as
73 * Reserved and should not be modified.
74 *
75 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
76 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
77 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
78 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
79 * access to trace functionality is not supported, this bit is RES0.
80 * CPTR_EL3.TFP: This causes instructions that access the registers
81 * associated with Floating Point and Advanced SIMD execution to trap
82 * to EL3 when executed from any exception level, unless trapped to EL1
83 * or EL2.
84 * ---------------------------------------------------------------------
85 */
86 mrs x0, cptr_el3
87 bic w0, w0, #TCPAC_BIT
88 bic w0, w0, #TTA_BIT
89 bic w0, w0, #TFP_BIT
90 msr cptr_el3, x0
91
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000092 /* ---------------------------------------------
93 * Enable the instruction cache.
94 * ---------------------------------------------
95 */
96 mrs x0, sctlr_el3
97 orr x0, x0, #SCTLR_I_BIT
98 msr sctlr_el3, x0
99
100 isb
101
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102_wait_for_entrypoint:
103 /* ---------------------------------------------
104 * Find the type of reset and jump to handler
105 * if present. If the handler is null then it is
106 * a cold boot. The primary cpu will set up the
107 * platform while the secondaries wait for
108 * their turn to be woken up
109 * ---------------------------------------------
110 */
111 bl read_mpidr
112 bl platform_get_entrypoint
113 cbnz x0, _do_warm_boot
114 bl read_mpidr
115 bl platform_is_primary_cpu
116 cbnz x0, _do_cold_boot
117
118 /* ---------------------------------------------
119 * Perform any platform specific secondary cpu
120 * actions
121 * ---------------------------------------------
122 */
123 bl plat_secondary_cold_boot_setup
124 b _wait_for_entrypoint
125
126_do_cold_boot:
127 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000128 * Init C runtime environment.
129 * - Zero-initialise the NOBITS sections.
130 * There are 2 of them:
131 * - the .bss section;
132 * - the coherent memory section.
133 * - Copy the data section from BL1 image
134 * (stored in ROM) to the correct location
135 * in RAM.
136 * ---------------------------------------------
137 */
138 ldr x0, =__BSS_START__
139 ldr x1, =__BSS_SIZE__
140 bl zeromem16
141
142 ldr x0, =__COHERENT_RAM_START__
143 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
144 bl zeromem16
145
146 ldr x0, =__DATA_RAM_START__
147 ldr x1, =__DATA_ROM_START__
148 ldr x2, =__DATA_SIZE__
149 bl memcpy16
150
151 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100152 * Initialize platform and jump to our c-entry
153 * point for this type of reset
154 * ---------------------------------------------
155 */
156 adr x0, bl1_main
157 bl platform_cold_boot_init
158 b _panic
159
160_do_warm_boot:
161 /* ---------------------------------------------
162 * Jump to BL31 for all warm boot init.
163 * ---------------------------------------------
164 */
165 blr x0
166_panic:
167 b _panic