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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <asm_macros.S>
Dan Handley97043ac2014-04-09 13:14:54 +010033#include <psci.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35 .globl psci_aff_on_finish_entry
36 .globl psci_aff_suspend_finish_entry
37 .globl __psci_cpu_off
38 .globl __psci_cpu_suspend
Achin Gupta317ba092014-05-09 19:32:25 +010039 .globl psci_power_down_wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 /* -----------------------------------------------------
42 * This cpu has been physically powered up. Depending
43 * upon whether it was resumed from suspend or simply
44 * turned on, call the common power on finisher with
45 * the handlers (chosen depending upon original state).
46 * For ease, the finisher is called with coherent
47 * stacks. This allows the cluster/cpu finishers to
48 * enter coherency and enable the mmu without running
49 * into issues. We switch back to normal stacks once
50 * all this is done.
51 * -----------------------------------------------------
52 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +000053func psci_aff_on_finish_entry
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 adr x23, psci_afflvl_on_finishers
55 b psci_aff_common_finish_entry
56
57psci_aff_suspend_finish_entry:
58 adr x23, psci_afflvl_suspend_finishers
59
60psci_aff_common_finish_entry:
61 adr x22, psci_afflvl_power_on_finish
Achin Guptab739f222014-01-18 16:50:09 +000062
63 /* ---------------------------------------------
Andrew Thoelke5e910072014-06-02 11:40:35 +010064 * Initialise the pcpu cache pointer for the CPU
65 * ---------------------------------------------
66 */
67 bl init_cpu_data_ptr
68
69 /* ---------------------------------------------
Achin Guptab739f222014-01-18 16:50:09 +000070 * Exceptions should not occur at this point.
71 * Set VBAR in order to handle and report any
72 * that do occur
73 * ---------------------------------------------
74 */
75 adr x0, early_exceptions
76 msr vbar_el3, x0
77 isb
78
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000079 /* ---------------------------------------------
80 * Use SP_EL0 for the C runtime stack.
81 * ---------------------------------------------
82 */
83 msr spsel, #0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000084
Andrew Thoelke7935d0a2014-04-28 12:32:02 +010085 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 bl platform_set_coherent_stack
87
88 /* ---------------------------------------------
89 * Call the finishers starting from affinity
90 * level 0.
91 * ---------------------------------------------
92 */
Andrew Thoelke7935d0a2014-04-28 12:32:02 +010093 mrs x0, mpidr_el1
Achin Guptaa45e3972013-12-05 15:10:48 +000094 bl get_power_on_target_afflvl
95 cmp x0, xzr
96 b.lt _panic
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 mov x3, x23
98 mov x2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 mov x1, #MPIDR_AFFLVL0
Andrew Thoelke7935d0a2014-04-28 12:32:02 +0100100 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101 blr x22
Achin Gupta4f6ad662013-10-25 09:08:21 +0100102
103 /* --------------------------------------------
104 * Give ourselves a stack allocated in Normal
105 * -IS-WBWA memory
106 * --------------------------------------------
107 */
Andrew Thoelke7935d0a2014-04-28 12:32:02 +0100108 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100109 bl platform_set_stack
110
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000111 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112_panic:
113 b _panic
114
115 /* -----------------------------------------------------
116 * The following two stubs give the calling cpu a
117 * coherent stack to allow flushing of caches without
118 * suffering from stack coherency issues
119 * -----------------------------------------------------
120 */
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000121func __psci_cpu_off
Achin Gupta4f6ad662013-10-25 09:08:21 +0100122 func_prologue
123 sub sp, sp, #0x10
124 stp x19, x20, [sp, #0]
125 mov x19, sp
Andrew Thoelke7935d0a2014-04-28 12:32:02 +0100126 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 bl platform_set_coherent_stack
128 bl psci_cpu_off
Achin Gupta4f6ad662013-10-25 09:08:21 +0100129 mov sp, x19
130 ldp x19, x20, [sp,#0]
131 add sp, sp, #0x10
132 func_epilogue
133 ret
134
Andrew Thoelke0a30cf52014-03-18 13:46:55 +0000135func __psci_cpu_suspend
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136 func_prologue
137 sub sp, sp, #0x20
138 stp x19, x20, [sp, #0]
139 stp x21, x22, [sp, #0x10]
140 mov x19, sp
141 mov x20, x0
142 mov x21, x1
143 mov x22, x2
Andrew Thoelke7935d0a2014-04-28 12:32:02 +0100144 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145 bl platform_set_coherent_stack
146 mov x0, x20
147 mov x1, x21
148 mov x2, x22
149 bl psci_cpu_suspend
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150 mov sp, x19
151 ldp x21, x22, [sp,#0x10]
152 ldp x19, x20, [sp,#0]
153 add sp, sp, #0x20
154 func_epilogue
155 ret
156
Achin Gupta317ba092014-05-09 19:32:25 +0100157 /* --------------------------------------------
158 * This function is called to indicate to the
159 * power controller that it is safe to power
160 * down this cpu. It should not exit the wfi
161 * and will be released from reset upon power
162 * up. 'wfi_spill' is used to catch erroneous
163 * exits from wfi.
164 * --------------------------------------------
165 */
166func psci_power_down_wfi
Andrew Thoelke8cec5982014-04-28 12:28:39 +0100167 dsb sy // ensure write buffer empty
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168 wfi
169wfi_spill:
170 b wfi_spill
171