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Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta7c88f3f2014-02-18 18:09:12 +000031#include <arch_helpers.h>
Dan Handley97043ac2014-04-09 13:14:54 +010032#include <bl_common.h>
33#include <bl32.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000034#include <debug.h>
Dan Handley97043ac2014-04-09 13:14:54 +010035#include <platform.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000036#include <spinlock.h>
Dan Handley97043ac2014-04-09 13:14:54 +010037#include <stdio.h>
38#include <tsp.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000039
40/*******************************************************************************
Vikram Kanigiri6871c5d2014-05-16 18:48:12 +010041 * Declarations of linker defined symbols which will help us find the layout
42 * of trusted SRAM
43 ******************************************************************************/
44extern unsigned long __RO_START__;
45extern unsigned long __COHERENT_RAM_END__;
46
47/*******************************************************************************
Achin Gupta7c88f3f2014-02-18 18:09:12 +000048 * Lock to control access to the console
49 ******************************************************************************/
50spinlock_t console_lock;
51
52/*******************************************************************************
53 * Per cpu data structure to populate parameters for an SMC in C code and use
54 * a pointer to this structure in assembler code to populate x0-x7
55 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +010056static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000057
58/*******************************************************************************
59 * Per cpu data structure to keep track of TSP activity
60 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +010061static work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
Achin Gupta7c88f3f2014-02-18 18:09:12 +000062
63/*******************************************************************************
64 * Single reference to the various entry points exported by the test secure
65 * payload. A single copy should suffice for all cpus as they are not expected
66 * to change.
67 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +010068static const entry_info_t tsp_entry_info = {
Achin Gupta7c88f3f2014-02-18 18:09:12 +000069 tsp_fast_smc_entry,
70 tsp_cpu_on_entry,
71 tsp_cpu_off_entry,
72 tsp_cpu_resume_entry,
73 tsp_cpu_suspend_entry,
74};
75
Vikram Kanigiri6871c5d2014-05-16 18:48:12 +010076
77/*******************************************************************************
78 * The BL32 memory footprint starts with an RO sections and ends
79 * with a section for coherent RAM. Use it to find the memory size
80 ******************************************************************************/
81#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__)
82
83#define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
84
Dan Handleyfb037bf2014-04-10 15:37:22 +010085static tsp_args_t *set_smc_args(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +000086 uint64_t arg1,
87 uint64_t arg2,
88 uint64_t arg3,
89 uint64_t arg4,
90 uint64_t arg5,
91 uint64_t arg6,
92 uint64_t arg7)
93{
94 uint64_t mpidr = read_mpidr();
95 uint32_t linear_id;
Dan Handleyfb037bf2014-04-10 15:37:22 +010096 tsp_args_t *pcpu_smc_args;
Achin Gupta7c88f3f2014-02-18 18:09:12 +000097
98 /*
99 * Return to Secure Monitor by raising an SMC. The results of the
100 * service are passed as an arguments to the SMC
101 */
102 linear_id = platform_get_core_pos(mpidr);
103 pcpu_smc_args = &tsp_smc_args[linear_id];
104 write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0);
105 write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1);
106 write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2);
107 write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3);
108 write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4);
109 write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5);
110 write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6);
111 write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7);
112
113 return pcpu_smc_args;
114}
115
116/*******************************************************************************
117 * TSP main entry point where it gets the opportunity to initialize its secure
118 * state/applications. Once the state is initialized, it must return to the
119 * SPD with a pointer to the 'tsp_entry_info' structure.
120 ******************************************************************************/
121uint64_t tsp_main(void)
122{
123 uint64_t mpidr = read_mpidr();
124 uint32_t linear_id = platform_get_core_pos(mpidr);
125
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126 /* Initialize the platform */
127 bl32_platform_setup();
128
129 /* Initialize secure/applications state here */
130
131 /* Update this cpu's statistics */
132 tsp_stats[linear_id].smc_count++;
133 tsp_stats[linear_id].eret_count++;
134 tsp_stats[linear_id].cpu_on_count++;
135
136 spin_lock(&console_lock);
Jon Medhurstfb052462014-02-17 12:18:24 +0000137 printf("TSP %s\n\r", build_message);
Vikram Kanigiri6871c5d2014-05-16 18:48:12 +0100138 INFO("Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE);
139 INFO("Total memory size : 0x%x bytes\n",
140 (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE));
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000141 INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr,
142 tsp_stats[linear_id].smc_count,
143 tsp_stats[linear_id].eret_count,
144 tsp_stats[linear_id].cpu_on_count);
145 spin_unlock(&console_lock);
146
147 /*
148 * TODO: There is a massive assumption that the SPD and SP can see each
149 * other's memory without issues so it is safe to pass pointers to
150 * internal memory. Replace this with a shared communication buffer.
151 */
152 return (uint64_t) &tsp_entry_info;
153}
154
155/*******************************************************************************
156 * This function performs any remaining book keeping in the test secure payload
157 * after this cpu's architectural state has been setup in response to an earlier
158 * psci cpu_on request.
159 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +0100160tsp_args_t *tsp_cpu_on_main(void)
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000161{
162 uint64_t mpidr = read_mpidr();
163 uint32_t linear_id = platform_get_core_pos(mpidr);
164
165 /* Update this cpu's statistics */
166 tsp_stats[linear_id].smc_count++;
167 tsp_stats[linear_id].eret_count++;
168 tsp_stats[linear_id].cpu_on_count++;
169
170 spin_lock(&console_lock);
171 printf("SP: cpu 0x%x turned on\n\r", mpidr);
172 INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr,
173 tsp_stats[linear_id].smc_count,
174 tsp_stats[linear_id].eret_count,
175 tsp_stats[linear_id].cpu_on_count);
176 spin_unlock(&console_lock);
177
178 /* Indicate to the SPD that we have completed turned ourselves on */
179 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
180}
181
182/*******************************************************************************
183 * This function performs any remaining book keeping in the test secure payload
184 * before this cpu is turned off in response to a psci cpu_off request.
185 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +0100186tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000187 uint64_t arg1,
188 uint64_t arg2,
189 uint64_t arg3,
190 uint64_t arg4,
191 uint64_t arg5,
192 uint64_t arg6,
193 uint64_t arg7)
194{
195 uint64_t mpidr = read_mpidr();
196 uint32_t linear_id = platform_get_core_pos(mpidr);
197
198 /* Update this cpu's statistics */
199 tsp_stats[linear_id].smc_count++;
200 tsp_stats[linear_id].eret_count++;
201 tsp_stats[linear_id].cpu_off_count++;
202
203 spin_lock(&console_lock);
204 printf("SP: cpu 0x%x off request\n\r", mpidr);
205 INFO("cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr,
206 tsp_stats[linear_id].smc_count,
207 tsp_stats[linear_id].eret_count,
208 tsp_stats[linear_id].cpu_off_count);
209 spin_unlock(&console_lock);
210
211
Achin Gupta607084e2014-02-09 18:24:19 +0000212 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000213 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
214}
215
216/*******************************************************************************
217 * This function performs any book keeping in the test secure payload before
218 * this cpu's architectural state is saved in response to an earlier psci
219 * cpu_suspend request.
220 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +0100221tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000222 uint64_t arg1,
223 uint64_t arg2,
224 uint64_t arg3,
225 uint64_t arg4,
226 uint64_t arg5,
227 uint64_t arg6,
228 uint64_t arg7)
229{
230 uint64_t mpidr = read_mpidr();
231 uint32_t linear_id = platform_get_core_pos(mpidr);
232
233 /* Update this cpu's statistics */
234 tsp_stats[linear_id].smc_count++;
235 tsp_stats[linear_id].eret_count++;
236 tsp_stats[linear_id].cpu_suspend_count++;
237
238 spin_lock(&console_lock);
239 printf("SP: cpu 0x%x suspend request. power state: 0x%x\n\r",
240 mpidr, power_state);
241 INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr,
242 tsp_stats[linear_id].smc_count,
243 tsp_stats[linear_id].eret_count,
244 tsp_stats[linear_id].cpu_suspend_count);
245 spin_unlock(&console_lock);
246
Achin Gupta607084e2014-02-09 18:24:19 +0000247 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000248 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
249}
250
251/*******************************************************************************
252 * This function performs any book keeping in the test secure payload after this
253 * cpu's architectural state has been restored after wakeup from an earlier psci
254 * cpu_suspend request.
255 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +0100256tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000257 uint64_t arg1,
258 uint64_t arg2,
259 uint64_t arg3,
260 uint64_t arg4,
261 uint64_t arg5,
262 uint64_t arg6,
263 uint64_t arg7)
264{
265 uint64_t mpidr = read_mpidr();
266 uint32_t linear_id = platform_get_core_pos(mpidr);
267
268 /* Update this cpu's statistics */
269 tsp_stats[linear_id].smc_count++;
270 tsp_stats[linear_id].eret_count++;
271 tsp_stats[linear_id].cpu_resume_count++;
272
273 spin_lock(&console_lock);
274 printf("SP: cpu 0x%x resumed. suspend level %d \n\r",
275 mpidr, suspend_level);
276 INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr,
277 tsp_stats[linear_id].smc_count,
278 tsp_stats[linear_id].eret_count,
279 tsp_stats[linear_id].cpu_suspend_count);
280 spin_unlock(&console_lock);
281
Achin Gupta607084e2014-02-09 18:24:19 +0000282 /* Indicate to the SPD that we have completed this request */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000283 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
284}
285
286/*******************************************************************************
287 * TSP fast smc handler. The secure monitor jumps to this function by
288 * doing the ERET after populating X0-X7 registers. The arguments are received
289 * in the function arguments in order. Once the service is rendered, this
290 * function returns to Secure Monitor by raising SMC
291 ******************************************************************************/
Dan Handleyfb037bf2014-04-10 15:37:22 +0100292tsp_args_t *tsp_fast_smc_handler(uint64_t func,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000293 uint64_t arg1,
294 uint64_t arg2,
295 uint64_t arg3,
296 uint64_t arg4,
297 uint64_t arg5,
298 uint64_t arg6,
299 uint64_t arg7)
300{
Achin Gupta916a2c12014-02-09 23:11:46 +0000301 uint64_t results[2];
302 uint64_t service_args[2];
303 uint64_t mpidr = read_mpidr();
304 uint32_t linear_id = platform_get_core_pos(mpidr);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000305
Achin Gupta916a2c12014-02-09 23:11:46 +0000306 /* Update this cpu's statistics */
307 tsp_stats[linear_id].smc_count++;
308 tsp_stats[linear_id].eret_count++;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000309
Achin Gupta916a2c12014-02-09 23:11:46 +0000310 printf("SP: cpu 0x%x received fast smc 0x%x\n", read_mpidr(), func);
311 INFO("cpu 0x%x: %d smcs, %d erets\n", mpidr,
312 tsp_stats[linear_id].smc_count,
313 tsp_stats[linear_id].eret_count);
314
315 /* Render secure services and obtain results here */
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000316
317 results[0] = arg1;
318 results[1] = arg2;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000319
320 /*
321 * Request a service back from dispatcher/secure monitor. This call
322 * return and thereafter resume exectuion
323 */
324 tsp_get_magic(service_args);
325
326 /* Determine the function to perform based on the function ID */
327 switch (func) {
328 case TSP_FID_ADD:
329 results[0] += service_args[0];
330 results[1] += service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000331 break;
332 case TSP_FID_SUB:
333 results[0] -= service_args[0];
334 results[1] -= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000335 break;
336 case TSP_FID_MUL:
337 results[0] *= service_args[0];
338 results[1] *= service_args[1];
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000339 break;
340 case TSP_FID_DIV:
341 results[0] /= service_args[0] ? service_args[0] : 1;
342 results[1] /= service_args[1] ? service_args[1] : 1;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000343 break;
344 default:
345 break;
346 }
347
Achin Gupta916a2c12014-02-09 23:11:46 +0000348 return set_smc_args(func,
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000349 results[0],
350 results[1],
Achin Gupta916a2c12014-02-09 23:11:46 +0000351 0, 0, 0, 0, 0);
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000352}
353